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Sunday, July 12, 2020 | |||
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8:30am-9:30am | REGISTRATIONS | ||
TRACKS | TRACK 1 Session Chair: Sameer Chillarige | TRACK 2 Session Chair: Jais Abraham | TRACK 3 Session Chair: Shamitha Rao |
HALL NAME | Zoom Meeting | Zoom Meeting | Zoom Meeting |
9:30 am – 11:00 am (15 mins. Break) 11:15 am – 12:45 pm | T1: Digital Circuit Testing – A Tutorial for Beginners Prof. Indranil Sengupta (IIT, Kharagpur) | T2: Design and Consumption of IPs for Fail-Safe Automotive IC’s Nilanjan Mukherjee, Lee Harrison, Tom Waayers, Antonio Priore, Raghav Mehta (Mentor, a Siemens Business) | T3: Scan Test escapes, new fault models, and the growing need for functional system level tests Prof. Adit Singh (Auburn University) |
12:45pm-1:45pm | BREAK | ||
1:45 pm – 3:15 pm (15 mins. Break) 3:30 pm – 5:00 pm |
T4: Cost Effective DFT and Test for Embedded Analog Rubin Parekhji, Malav Shah (Texas Instruments) |
T5: Power-aware testing in the era of IOT Patrick GIRARD (LIRMM), Prof. Xiaoqing WEN (Kyushu Institute of Technology) | T6: Fast & Furious High Speed I/O (NRZ MHz to PAM4 GHz) and its ATE Challenges Jagadish Chandrasekaran, Srinivasan Chandrasekaran, Gowrishankar Ilankumaran (Tessolve) |
Monday, July 13, 2020 | ||
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8:00am-9:00am
| REGISTRATIONS | |
9:00am-9:15am
| Inauguration/Welcome | Navin Bishnoi, General Chair, ITC India 2020
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9:15am-10:00am
| Keynote 1: “Keys to Hardware Security and Test” | Deirdre Hanford, Chief Security Officer, Synopsys
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10:00am-10:45am
| Keynote 2: “Managing Test Coverage and Quality across a Diverse Portfolio Using a Data-Centric Approach” | Dr. Ken Butler, DFT/Test/Reliability/Software Engineer and Data Scientist
Texas Instrument, Dallas, USA
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10:45am-11:15am
| BREAK
| |
SESSIONS
| Session 1 – 3D Stacked IC Test
Session Chair : Srinivas Vooka | Session 2 – Post-Silicon , Validation & Characterization
Session Chair : Venkata Totakura |
HALL NAME | Zoom Meeting | Zoom Meeting |
11:15am-12:45pm
| 1.1 Machine Learning based Temperature Estimation for Test Scheduling of 3D ICs 1.2 Validating and Characterizing a 2.5D High Bandwidth Memory SubSystem 1.3 Built-In Self-Repair for Manufacturing and Runtime TSV Defects in 3D ICs | 2.1 Machine Learning Driven Throughput Optimization of Volume Diagnosis Methodology Sameer Chillarige, Anil Malik, Atul Chhabra, Bharath Nandakumar, Martin Amodeo, 2.2 A Critical Engineering Dissection of LOS and LOC At-speed Test Approaches 2.3 Wavelet transform based fault diagnosis in analog circuits with SVM classifier |
12:45pm-1:45pm
| BREAK
| |
SESSIONS
| Test Reality Check (TRC) Track
Session Chair | Kavitha Shankar | |
HALL NAME | Zoom Meeting | |
1:45pm-2:45pm
| TRC1.1 A Practical Approach to DFT Implementation on Fully Abutted Designs TRC1.2 Clock Control and Integration of a High Speed SerDes macro – A Design for Test Standpoint TRC1.3 Techniques to Reduce ASIC logic Scan Test Cost TRC1.4 Simultaneous Scan & MBIST Testing | |
2:45pm-3:00pm
| BREAK
| |
SESSIONS
| Panel Discussion Session Chair | Kamlesh Pandey | |
HALL NAME | Zoom Meeting | |
3:00pm-4:00pm
| Topic: Are advanced fault models (cell aware, layout aware, timing aware etc.) more relevant during nascent stage of process technology nodes? Carl Wisnesky (Cadence), Prasad Mantri (Tessolve), Dhivakaran Santhanam (Broadcom), Abhishek Chaudhary (Rambus) | |
4:00pm
| Closing – End of Day 1
| |
Tuesday, July 14, 2020 | ||
|---|---|---|
8:00am-9:00am
| REGISTRATIONS | |
9:00am-9:15am
| Welcome | Navin Bishnoi, General Chair, ITC India 2020 ITC US and TTTC Update | Yervant Zorian, President TTTC | |
9:15am-10:00am
| Keynote 3: “Architecting a software-defined car—from end to end and top to bottom” | Riccardo Mariani, VP Industry Safety, Nvidia
| |
10:00am-10:45am
| Keynote 4: “Silicon Lifecycle Challenges and the Expanding Role of Test
” | Brady Benware, Mentor A Siemens Business
| |
10:45am-11:15am
| BREAK
| |
SESSIONS
| Session 3 – Analog & Emerging Circuits DFT Session Chair : Srinivas Vooka | Session 4 – Test Security & DFT Verification Session Chair : Venkata Totakura |
HALL NAME | Zoom Meeting | Zoom Meeting |
11:15am-12:45pm
| 3.1 Resource Optimal Realization of Fault-Tolerant Quantum Circuit 3.2 Analyzing Fault Tolerance Behaviour in Memristor-based Crossbar for Neuromorphic Applications 3.3 Fault Vulnerability Ranking of Transistors in Analog Integrated Circuits using AC Analysis | 4.1 An Efficient Hardware Trojan Detection Approach adopting Testability Based Features 4.2 Concealing Test Compression Mechanisms from Security Attacks 4.3 A non-ICL UVM approach to verifying DFx IJTAG network and its pros and cons versus the ICL-PDL approach |
12:45pm-1:45pm
| BREAK | |
SESSIONS
| Academia Research Track (ART) Session Chair | Ankush Srivastava | |
HALL NAME | Zoom Meeting | |
1:45pm-2:45pm
| ART1.1 Genetic Algorithm based Hardware Trojan Detection and Logical Masking ART1.2 A Hash based Secure Scheme (HSS) against scan-based attacks on AES cipher ART1.3 Modeling and test generation for combinational hardware trojans ART1.4 Efficient Fault Detection and Diagnosis of Digital Microfluidic Biochip Using Multiple Electrodes Actuation | |
2:45pm-3:00pm
| BREAK
| |
SESSIONS
| Special Session Session Chair | Subhadip Kundu | |
HALL NAME | Zoom Meeting | |
3:00pm-4:00pm
| Topic: Automated Test Equipment for Automotive SoCs Anuruddh Sachan (NXP), Akhil Jain (NXP) | |
4:00pm-4:10pm
| Closing
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