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Scientific Director at imec (Leuven, Belgium)
Visiting Researcher at Eindhoven University of Technology (Eindhoven, the Netherlands)
Erik Jan Marinissen is Scientific Director at imec in Leuven, Belgium, where he is responsible for research on test and design-for-test, covering topics as diverse as TSV-based 3D-stacked ICs, silicon photonics, CMOS technology nodes below 10nm, and STT-MRAMs. In addition, he is Visiting Researcher at Eindhoven University of Technology (TU/e), the Netherlands. Previously, he worked at NXP Semiconductors and Philips Research Laboratories in Eindhoven, Nijmegen, and Sunnyvale. Marinissen holds an MSc degree in Computing Science (1990) and a PDEng degree in Software Technology (1992), both from TU/e. He is (co-)author of 275+ journal and conference papers and (co-)inventor of eighteen US/EP patents.
Marinissen served as Editor-in-Chief of IEEE Std 1500™-2005 on embedded core test access and as Founder and Chair (currently Vice-Chair) of IEEE Std 1838™-2019 on 3D test access. Marinissen is founder of the workshops ‘Diagnostic Services in Network-on-Chips’ (2007-2011), ‘3D Integration Workshop’ (2009-2013), and the IEEE International Workshop on Testing Three-Dimensional Stacked ICs’ (2010-2015). He has been Program Chair of DDECS 2002, ETS 2006, 3D-TEST 2009-15, and DATE 2013, and General Chair of ETW 2003, DSNOC 2007-08, 3DIW 2009-10, and serves on numerous conference committees, including ATS, DATE, ETS, ITC, ITC-Asia, and VTS. He serves on the editorial boards of IEEE ‘Design & Test’ and Springer’s ‘Journal of Electronic Testing: Theory and Applications’.
On its 50th anniversary, ITC announced Marinissen to be the most-cited author of ITC papers published in the most recent 25-year period 1995-2019. Marinissen is recipient of the Most Significant Paper Awards at the IEEE International Test Conference (ITC) 2008 and 2010, Best Paper Awards at the Chrysler-Delco-Ford Automotive Electronics Reliability Workshop 1995 and the IEEE International Board Test Workshop (BTW) 2002, the Most Inspirational Presentation Award at the Semiconductor Wafer Test Workshop (SWTW) 2013, the HiPEAC Technology Transfer Award 2015, the SEMI Best ATE Paper Award 2016, the National Instruments’ Engineering Impact Award 2017, the IEEE Standards Association’s Emerging Technology Award 2017, Best Paper Award at the International Wafer-Level Packaging Conference (IWLPC) 2018, and the Best Design-Track Paper Award at the Design, Automation, and Test in Europe (DATE) Conference 2020.
Marinissen is Fellow of IEEE, Golden Core Member of IEEE Computer Society, and serves as elected member of the IEEE Computer Society’s Board of Governors for the term 2019-2021. Marinissen has presented full- and half-day tutorials on Core-Based SOC Test, 3D-SIC Test, and Improving ATPG Test Quality at 3DIC, 3D-ASIP, DATE, ETS/ETW, ITC, ITC-Asia, and VTS, as well as numerous multi-day in-house company courses. During the span of his career, Marinissen has supervised 45+ international MSc and PhD students, many of which are still working in the international DfT and test community at companies including Altran (SE), Apple (USA), ASML (NL), Axians (NL), Cadence Design Systems (TW and USA), Chinese University in Hong Kong (HK), Cyclomedia (NL), Espros Photonics (CH), Fish & Richardson P.C. (USA), Den Hartogh Logistics (NL), Hong Kong Polytecnic University (HK), Howlogy (NL), imec (BE), Intel (USA), Intel Labs (USA), NXP Semiconductors (NL), Philips (NL), Prodrive Technologies (NL), Pontifícia Universidade Católica do Rio Grande do Sul (BR), Realtek (TW), Rohaco Industrial Handling (NL), Semcon (SE), Soft Machine (RO), Sony Mobile Communications (SE), Testonica Labs (EE), Texas Instruments (IN), TSMC (TW and USA), and u-blox (GR).
Carl holds a Bachelor’s degree in Computer Engineering from Penn State University and both a Master’s Degree in Electrical Engineering and an MBA from Binghamton University in New York, USA. He has nearly 20 years of experience in design, test, and verification working at IBM’s Test Design and Automation group, Lockheed Martin’s Advanced Unmanned Aerial Vehicles team, and Cadence Design Systems. He is working in the areas of Fault Modeling, Quality of Silicon, and Hierarchical Test at Cadence. Carl’s contributions include multiple papers and patents in the areas of test.
M.S in Advanced VLSI from Northwestern Polytechnic University, Fremont 2008
Worked for 5 years at Analog Devices from 2000 to 2005, Santa Clara leading flow and methodology for
front-end lint, synthesis, formal-verification and STA.
Joined BRCM in 2006 – Worked on flow and methodology for front-end lint, synthesis, formalverification and STA until 2012 supporting multi-million transistor designs.
Moved to DFT in 2012 with focus on SCAN-ATPG/LBIST implementation, verification and silicon
validation currently managing a team of 8 serving the needs of both India design centre as well as San
Jose design centre.
Currently is the DFT architect managing DFT team at Tessolve Semiconductor, He heads VLSI digital design Center of Excellence at Tessolve and manages DFT team at Tessolve. Prasad has 25+ years of design and DFT experience in major semiconductor companies including Sun Microsystems / Oracle (13yrs), Micron Technologies, Synopsys Inc (3yrs), Silicon Graphics Inc (4yrs) along with other startups.
Contributed to the DFT and Yield enhancement of multi-generation Sparc microprocessors from 2003 to 2017. Worked on DFT for the Nintendo 64 core chipsets. Coauthored multiple conference papers. Has one patent.
General co- Chair International Test Conference India 2017-2019. Invited to be on Technical Program Committee of TTTC Test Technology Educational Program (TTEP) 2019 of IEEE. Contributed to the ITRS Test technology roadmap from 2007 to 2010. Co-Author of IEEE white papers on Universal Internet access.
Abhishek Chaudhary is well known leader in DFT community with a proven track record in industry. He has worked at Freescale, a leading company in the automotive segment and is currently leading the DFT mission at Rambus. He has built a strong DFT team with expertise in delivering High Speed SerDes, HBM & GDDR IPs and memory interface chip solutions across Rambus worldwide. He received his Masters degree from IIT Delhi and is pursuing his PhD along with his current job.
Abhishek is passionate about bridging the industry-academia gap in India. He is vice-chair of TTTC India and is a seasoned presenter in TTTC events and other industry conferences along with a patent portfolio.
Kamlesh is currently working as Technical Director and Distinguished Engineer at Broadcom Inc., Bangalore, wherein he leads a team working on DFT architecture, DFT flow development and DFT implementation on Settop box and DOCSIS SOCs. He joined Broadcom in 2004. Prior to joining Broadcom, he was DFT engineer at Cisco Systems. He has over 20 years of experience spanning across all aspects of DFT. His contribution in the field of research includes two US patents and invention of inhouse at-speed test architecture known as CTSA.
Kamlesh has architected and designed secure JTAG and boundary scan, In-house Logic BIST for security processor, Analog BIST for Video DAC, Loopback based DDR BIST, JTAG based scandump for functional debug, and JTAG based low pin count scan testing. His areas of interest are defect based testing, atspeed test architecture, scan compression, analog and mixed signal testing, ultra-low cost testing. He has received M.Tech. in Microelectronic and VLSI systems from Indian Institute of Technology Kanpur, India in year 2001.