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International Test Conference the world’s premier venue dedicated to the electronic test of devices, boards and systems, will for the first time host a dedicated Test Reality Check (TRC) track.
Important Dates
The objective of this track is to provide an informal platform for Chip Designers, EDA solution providers as well as academia to present their success stories, state specific burning test issues of their respective product lines and debate about any specific test topic of interest to test community at large The TRC track comprises of the following three sections
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Authors are invited to submit a crisp power point presentation regarding their talk for this track The presentations from this track will not be published in IEEE Explore as part of ITC main conference proceedings
TRC Track Co-Chairs:
Design for test
Built-in self test
ATPG and defect-oriented test
Delay test
Low power design and test
Instruction-based self test
On-line test methodology
Reliability of CMOS circuits
Self checker circuits
Self-diagnosis methods
Defect-Oriented Testing
Fault tolerant micro-architecture
Self-healing system design
Energy and performance aware
fault tolerant micro architectures
Device degradation and mitigation
System validation methodology
Design for reliability, dependability,
and verifiability
DFM and Test Diagnosis
Emerging Defect Mechanisms
Hardware Security and Trust
IoT Testing
Memory Test and Repair
MEMS Testing
Mixed-Signal and Analog Test
On-Chip Test Compression
Online Test
Pre-and Post Silicon Validation
Power Issues in Test
SoC/SiP/NoC Test
Silicon Debug
Jitter, High-Speed I/O and RF Test
Simulation and Test
Timing Test
Yield Analysis and Optimization