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Please note: We require the authors to follow this paper template: https://www.ieee.org/content/dam/ieee-org/ieee/web/org/conferences/Conference-template-A4.doc
The Call For Submission for Academia Research Track 2020 is live!
Authors are invited to submit truly innovative and “out-of-the-box” ideas that may not yet have been fully developed for presentation at reviewed conferences to address design and test related challenges. The idea of Academia Research Track (ART) is to manifest and publish creative research ideas from students and young academicians. The key objective of this track, for the first time planned to be held with the International Test Conference, is to provide a dedicated informal forum for vigorous creative discussion and debate of this area from researchers of various academic institutes. Please follow the submission guidelines as mentioned below.
Additional Benefits: Registration fee waiver and partial (or) full travel support will be provided through fellowship
Note: For detailed information about the submission process, requirements and deadlines, the selection process and any other questions regarding the program itself or contact information, please consult the ITC India website, or email the program chair at [email protected]
ITC India invites submissions from students, young researchers and academicians to publish their novel ideas on the latest advances in test, verification, diagnosis of ICs, boards and systems.
Design for test
Built-in self-test
ATPG and defect-oriented test
Delay test
Low power design and test
Instruction-based self-test
On-line test methodology
Reliability of CMOS circuits
Self-checker circuits
Self-diagnosis methods
Defect-Oriented Testing
Fault tolerant micro-architecture
Self-healing system design
Device degradation and mitigation
System validation methodology
Design for reliability, dependability, and verifiability
DFM and Test Diagnosis
Emerging Defect Mechanisms
Hardware Security and Trust
IoT Testing
Memory Test and Repair
MEMS Testing
Mixed-Signal and Analog Test
On-Chip Test Compression
Power Issues in Test
SoC/SiP/NoC Test
Silicon Debug
Power Issues in Test
SoC/SiP/NoC Test
Silicon Debug
Jitter, High-Speed I/O and RF Test
Simulation and Test
Timing Test
Yield Analysis and Optimization
Online Test
Pre- and Post- Silicon Validation
Energy and performance aware fault- tolerant micro-architectures