loader image
2018-ITC-logo-2-1-975x1024
Menu

Call for Fellowship

The 4th IEEE International Test Conference India (ITC India 2020) invites Students, Research Scholars and Faculty members working in the relevant fields of VLSI Design and Test for applying for the fellowship programme. ITC India has been offering generous fellowships to students and teachers of various Indian academic institutions. The fellowship provides complimentary registration to attend all the Tutorials, Keynotes and Technical Sessions.

At ITC India, design, test, and yield professionals can confront challenges faced by the industry, and learn how these challenges are being addressed by the combined efforts of academia, design tool and equipment suppliers, designers, and test engineers.

The Conference
Overview
Read Blog
View Gallery
Latest Agenda
Keynote
Tutorial Program
Submissions
Call for Papers
Call for Tutorials
Test Reality Check Track
Academia Research Track

Important Dates

• Last date for submitting application: 5th July 2020
• Notification for award of fellowship: 8th July 2020.

http://bit.do/itc-india-fellowship-2020

General Information
Committee
Contact Us
Archives
2017 Archives
2018 Archives
2019 Archives

Application Process:

  • We will be using an entirely online application process. A Gmail account is required for submitting the application http://bit.do/itc-india-fellowship-2020
  • Applications will be considered on first-come first-served basis.
  • Faculty members, Research scholars and students should upload the scanned copy of their Institution Identity card along with application.
  • Please submit only one form per applicant.
Submit Application

Important Guidelines:

  • Research scholars, Students or faculty members whose paper is accepted in ITC India 2020, will get the preference for the award of fellowship.
  • Research scholars and Students applying for the fellowship award must be involved in research areas related to VLSI Design & Test.
  • The faculty members applying for the fellowship award must have been associated in teaching or guiding research projects in VLSI Design & Test and taken active part in conducting workshops or seminars in these areas.
  • It is imperative that the fellows attend tutorials and presentations on all the three days. A record of attendance would be maintained for the same. A minimum of 90% of attendance is required all the sessions is mandatory to receive a participation certificate.
  • E-Certificates for Participation will be issued to the Participants only after submitting the Feedback link immediately, which will be posted in the Chat box at the end of each session.

Contact:

Fellowship Co-Chairs

Dr. S.Sivanantham

VIT, Vellore

Dr. Sree Ranjani Rajendran

IIT Madras

2018-ITC-logo-2-1-975x1024
Linkedin Facebook-f

Submissions

Conference

Help