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Managing power consumption of circuits and systems is one of the most important challenges for the semiconductor industry in the era of IoT. Power management techniques are used today to control the power dissipation during functional operation. Since the application of these techniques has profound implications on manufacturing test, power-aware testing has become indispensable for low-power LSIs and IoT devices. This tutorial provides a comprehensive and practical coverage of power-aware testing. Its first part gives the background and discusses power issues during test. The second part provides comprehensive information on structural and algorithmic solutions for alleviating test-power-related problems. The third part outlines low-power design techniques and shows how low-power devices can be tested safely without affecting yield and reliability.
Patrick GIRARD received a M.Sc. degree in Electrical Engineering and a Ph.D. degree in Microelectronics from the University of Montpellier, France, in 1988 and 1992 respectively. He is currently Research Director at CNRS (French National Center for Scientific Research) and works in the Microelectronics Department of the Laboratory of Informatics, Robotics and Microelectronics of Montpellier (LIRMM) – France.
Patrick Girard is Director of the International Associated Laboratory « LAFISI » (French-Italian Research Laboratory on Hardware-Software Integrated Systems) created in 2012 by the CNRS and the University of Montpellier, France, with the Politecnico di Torino, Italy. Since 2006, he is deputy director of the French scientific network dedicated to research in the fields of System-on-Chip, Embedded Systems and Connected Objects (SOC2), a network composed of 1400 researchers. His research interests include all aspects of digital and memory circuit test and reliability, with emphasis on critical constraints such as timing and power. Robust design of neuromorphic circuits, test of approximate circuits, as well as machine learning for fault diagnosis are also part of his new research activities.
Patrick Girard is Technical Activities Chair of the Test Technology Technical Council (TTTC) of the IEEE Computer Society. From 2006 to 2010, he was Vice-Chair of the European TTTC (ETTTC) of the IEEE Computer Society. He has served on numerous conference committees including ACM/IEEE Design Automation Conference (DAC), ACM/IEEE Design Automation and Test in Europe (DATE), IEEE International Test Conference (ITC), IEEE VLSI Test Symposium (VTS), IEEE European Test Symposium (ETS), IEEE Asian Test Symposium (ATS), and IEEE Computer Society Annual Symposium on VLSI (ISVLSI).
Patrick Girard was the founder and Editor-in-Chief of the ASP Journal of Low Power Electronics (JOLPE). He is an Associate Editor of IEEE Transactions on Emerging Topics in Computing, IEEE Transactions on Aerospace and Electronic Systems and Journal of Electronic Testing (JETTA – Springer). He was formerly an Associate Editor of IEEE Transactions on Computers, IEEE Transactions on VLSI Systems and IEEE Transactions on CAD of Circuits and Systems.
Patrick Girard has been involved in several (29) European research projects, national research projects (ANR, FUI), and industrial research projects with major companies like Infineon Technologies, Intel, Atmel, ST-Ericsson, STMicroelectronics, etc.
Patrick Girard has supervised 39 PhD dissertations, and has published 7 books or book chapters, 75 journal papers, and more than 250 conference and symposium papers. He is co-author of 4 patents. He is a Fellow of the IEEE and a Golden Core Member of the IEEE Computer Society.
For more details, please see Patrick Girard’s web page at: http://www.lirmm.fr/~girard/
Xiaoqing WEN received a B.E. degree from Tsinghua University, China, in 1986, a M.E. degree from Hiroshima University, Japan, in 1990, and a Ph.D. degree from Osaka University, Japan, in 1993. He was an Assistant Professor with Akita University, Japan, frrom 1993 to 1997, and a Visiting Researcher with the University of Wisconsin–Madison, USA, from Oct. 1995 to Mar. 1996. He joined SynTest Technologies Inc., USA, in 1998, and served as its Vice President and Chief Technology Officer until 2003. He joined Kyushu Institute of Technology, Japan, in 2003, where he is currently a Professor of the Department of Computer Science and Networks. He founded Dependable Integarted Systems Research Center (DISC) at Kyushu Institute of Technology in 2013 and served as its Director until 2015. He is a Co-Founder and Co-Chair of Technical Activity Committee on Power-Aware Testing under Test Technology Technical Council (TTTC) of IEEE Computer Society. He is an Associate Editor for IEEE Transactions on Very Large Scale Integration Systems (TVLSI) and Journal of Electronic Testing: Theory and Applications (JETTA). He co-authored and co-edited two popular books, VLSI Test Principles and Architectures: Design for Testability (2006) and Power-Aware Testing and Test Strategies for Low Power Devices (2009). His research interests include design, test, and diagnosis of VLSI circuits. He holds 43 U.S. Patents and 14 Japan Patents. He received many best paper awards, including the 2008 Society Best Paper Award from the Infromation Systmes Society (ISS) of Institute of Electronics, Information and Communication Engineers (IEICE). He is a Fellow of IEEE for his contributions to tesing of integarted circuits, a Senior Member of Information Processing Society of Japan (IPSJ), and a Senior Member of IEICE.