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Tutorial-6

Title: Fast & Furious High Speed I/O (NRZ MHz to PAM4 GHz) and its ATE Challenges

Abstract:

  • Introduction & Recent Trends –> 5mins
    It is an amazing fact of Today’s technology that we are able to manufacture the Integrated Circuits(IC) with millions of transistors switching at Giga range clock rates and containing N-number of High-Speed I/O interfaces working at Multi-gigabit data rates.

    Obviously this Tutorial content would be the eye opening session not only for the Test Engineers but also for DFT Folks, Design Folks as well which could make them to come up with better productization Test Technique to get it done in ATE with High efficiency and low cost.

  • Journey from Low speed IO to High Speed IO –> 10mins
    This section will briefly cover the evolution from low speed digital to High speed digital (Eg:- How Ethernet evolved from MII to 400G PAM4 Ethernet interface) with basic knowledge and requirements in ATE Testing.

  • NRZ signaling & its challenges –> 60mins
    1. A brief overview on EYE parameter testing
    2. How to choose appropriate PRBS in High Speed I/O
    3. Various Equalization involved in NRZ
    4. When to choose Embedding/De-embedding

  • PAM4 Signaling & its challenges –> 45mins
    1. A brief overview on PAM4 EYE parameter testing
    2. How to choose appropriate PRBS/PRQS for PAM4 testing
    3. Various Equalization involved in PAM4

  • Brief about ATE Challenges on PAM4 Testing –> 30mins
    1. Need for Stacked ATE Test Fixtures
    2. Few FPGA based test proposals in PAM4 testing

  • Summary & Queries –> 15mins

Presenters:

Jagadish Kumar

Jagadish Kumar, Vice President–Centre of Excellence & Test Engineering, Tessolve Semiconductor Pvt. Ltd., Bangalore. Have more than two and half decades of experience in the field of Semiconductor-Test and Product Engineering. He has presented his paper in various international conferences like ITC-US-19, TUG-18, ITC-India, etc., He has worked in various leading Companies few of them are Alliance Semiconductor, STATS, Wipro Technologies. He is also a member of IEEE-India. He has led Test Projects across various domains like RF, Analog, Digital, Memory and High speed digital. He is an expert in providing End to End chip testing solution starting from DFT support to Production deployment. He is specialized in developing novel methodology for validating silicon in ATE. He has headed ATE, Product, Test, Characterization, Pattern Generation and Hardware Teams. He has designed various cutting edge Probe cards and ATE load boards. He has worked on various leading ATE giants like Advantest, Teradyne, Credence, LTX, etc.

Srinivasan.C

Srinivasan.C presently works for Tessolve Semiconductor Pvt. Ltd., Bangalore, India as Associate Director – Test Engineering. Has over nineteen years of experience in the field of Semiconductor-Test and Product Engineering. He is an expert in the area of developing ATE test solution for various multi core SoC. He has leaded the team to test recently launched power management SoCs. He is specialized in various ATEs like 93K, Sapphire, Catalyst, J750, U-Flex, etc. He has presented his paper in various international conferences like ITC-US-19, TUG-18, ITC-India, etc.,

GowriShankar.I

GowriShankar.I,  presently works  for  Tessolve  Semiconductor  Pvt.  Ltd,  Bangalore, India as a Test Lead. He is an M.Tech graduate from Anna University. He started his career as an Assistant Professor and worked as a RF Design and Test Engineer. He has an experience as a Test Engineer for first launched 5G modem SoC. He has published his manuscript on International Journal for Scientific and Engineering Research and presented his paper on International Conferences like ICDASDC-13, ITC-India, ITC-US-19, etc.

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