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This tutorial aims at understanding the increasing use of functional system level tests (SLTs) as an additional final defect screen before processor SOCs are shipped for assembly. For this, we take an in-depth look at traditional scan based Stuck-at and TDF tests to understand potential sources of test escapes. We also extensively discuss the effectiveness of new test generation methodologies such as Cell Aware, Gate Exhaustive, Transistor Stuck-Open, and Timing Aware in plugging these structural test holes. Based on this, we identify failures that can still remain undetected by low cost scan structural tests, and require the use of expensive functional SLTs to achieve desired defect levels. In conclusion, we suggest strategies to minimize use SLTs without affecting defect levels.
Adit Singh is James B. Davis Professor of Electrical and Computer Engineering at Auburn University, where he has served on the faculty since 1991. Earlier he has held faculty positions at the University of Massachusetts in Amherst, and Virginia Tech, in Blacksburg; and visiting professorships at the University of Freiburg, Germany, and the University of Tokyo, Japan. His research interests span all aspects of VLSI technology. He is particularly recognized for his pioneering contributions to statistical methods in test and adaptive testing. Dr. Singh has held leadership roles as General Chair/Co-Chair/Program Chair for dozens of VLSI design and test conferences, and continues to serve on the Steering and Program Committees of many major international conferences in test and design automation. He served two terms (2007-11) as Chair of the IEEE Test Technology Technical Council (TTTC), and (2011-2015) on the Board of Governors of the IEEE Council on Design Automation (CEDA). Dr. Singh holds a B.Tech in Electrical Engineering from IIT Kanpur, and the M.S. and Ph.D. from Virginia Tech. He was elected Fellow of IEEE in 2002.