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Tutorial-1

Title: Digital Circuit Testing – A Tutorial for Beginners

Abstract:

The tutorial is targeted to beginners with little or no prior knowledge in circuit testing, who wish to learn the basic concepts of digital testing so that they can pursue related R&D activities in the future. This will be extremely useful to attract raw talents to the broad area of testing, where a steady decline in interest has been observed over the years. Instead of going into too much technical details of the algorithms and their complexities, a conscious attempt shall be made to explain the concepts through examples and illustrations. The specific topics that would be covered include:

  1. Fault modeling and fault collapsing, with particular emphasis on stuck-at faults.
  2. Fault simulation techniques, where the methods of parallel, deductive and concurrent fault simulation shall be illustrated with examples.
  3. Automated test pattern generation, where instead of digging into the details of practical algorithms, the essential ideas shall be explained with the help of examples.
  4. Design for testability, where the method of scan chain shall be discussed in some detail, mentioning the advantages and the various overheads involved.
  5. Built-in self-test, where LFSR based pseudo-random pattern generation and response compaction shell be discussed in some detail.

Biodata of Presenter:

Indranil Sengupta

Indranil Sengupta obtained his B.Tech., M.Tech. and PhD degrees in Computer Science from the University of Calcutta in the years 1983, 1985 and 1990, respectively. He joined Indian Institute of Technology, Kharagpur, as a faculty member in 1988, in the Department of Computer Science and Engineering, where he is presently a Full Professor. He has been the former Heads of the Department of Computer Science and Engineering, and School of Information Technology. He has over 30 years of teaching and research experience, guided 22 PhD students and published over 200 papers in peer reviewed journals and conferences. He has served as the General Chairs of Asian Test Symposium 2005, INDOCRYPT 2007, and Reversible Computing (RC) 2017, as Program/Organizing Chairs in several conferences in the areas of VLSI design and information security, and delivered a number of invited and tutorial talks. His research interests include VLSI design and test, reversible and quantum computing, memristor-based logic synthesis, and network security. He is a Senior Member of the IEEE.