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The exponential growth of electronics in automobiles have stimulated significant innovation towards the development of advanced safety mechanisms. At the same time, as automotive ICs are being manufactured in lower technology nodes, maintaining high quality and reliability continues to challenge the safety targets. The usage of high quality IP becomes extremely important in the success of automotive IC design. To comply with ISO26262 and zero DPPM test quality, IP providers and consumers need to consider the impact of functional safety on test. This has initiated an inevitable collaboration between functionally safe electronics developers and technology providers to accomplish unparalleled safety and integrity of automotive ICs.
Lee Harrison is Automotive IC Test Solutions Manager, with Mentor, A Siemens Business. He has over 20 years of industry experience with Mentor DFT products and has been involved in the specification of new test features and methodologies for Mentor customers, delivering high quality DFT solutions. With a focus on Automotive, Lee is working to ensure that current and future DFT requirements of Mentor’s automotive customers are understood and met. Lee Received his BEng in MicroElectronic Engineering from Brunel University London in 1996.
Tom Waayers works for NXP semiconductors, as a Technical Director in the roles DfT Product Manager and Architect. He’s leading DfT for eXcellence in which he drives NXP In-House standard and method development. ” Tom started 25 years ago working on Core Based Test at Philips Research Laboratories, and worked on several Design and Test related items in the Automotive domain since then. Tom is past member of IEEE 1500 WG, co-author of more than 10 Conference papers, co-author of the “The Core Test Wrapper Handbook”, and holds 15 patents in Design and Test. His most recent work is in Limited Pin Test and Analog Test access.
Antonio Priore works for Arm, as a Director of Functional Safety. He’s leading the Arm Functional Safety Centre of Excellence where he is responsible for the definition of product development lifecycle supporting multiple safety standards (e.g. ISO 26262, IEC 61508, DO-254, DO-178C, etc.) across different projects. Antonio is a Chartered Engineer with a career spanning more than a decade in Functional Safety Engineering across different domains like Automotive, Aerospace, Industrial and Railway. He’s author of 2 papers and actively contributes to standardization efforts across ISO, SAE and IEEE. Antonio holds a Master Degree in Electronic Engineering from the University of Pisa, Italy.
Nilanjan Mukherjee is a Senior Engineering Director in the Design-to-Silicon division at Mentor, A Siemens business. He has been with Mentor for almost two decades, where he is involved in the research and development of key technologies in the areas of test compression, Logic BIST, Memory BIST, low power DFT, In-System testing, and memory diagnosis. Some of his major accomplishments include being a co-inventor and an architect of the Embedded Deterministic Test (EDT) technology for test compression, the VersaPoint Test Points technology to reduce ATPG pattern count and improve random pattern test coverage, a Low Power Hybrid EDT/Logic BIST scheme for automotive ICs, and the Observation Scan Technology to dramatically improve test application time for In-system Logic BIST. Currently, his focus is on developing new techniques and methodologies for improving the quality and reliability of automotive ICs. Prior to joining Mentor Graphics, he worked at Lucent Bell Laboratories in New Jersey.
As a researcher, Nilanjan has co-authored more than 80 technical papers for various conference proceedings and archival journals. He is a co-inventor of 52 US patents and several international patents. He has received numerous awards including the Siemens Digital Industries Software Invention of the year 2019, the Most Significant Paper Award at ITC 2012, the Best Paper Award at VLSI Design in 2009, the Donald O. Pederson Outstanding Paper Award from the IEEE Circuits and Systems Society in 2006, the Teruhiko Yamada Memorial Best Student Paper Award at ATS 2001, and the Best Paper Award at VTS 1995.
Nilanjan received a B.Tech. (Hons) degree from IIT, India, and a Ph.D. degree from McGill University, Canada. He has given tutorials and invited talks at DAC, ITC, VTS, ATS, and VLSI Design, and has offered many short term courses on DFT.
Raghav Mehta is a Technical Marketing Engineer at Mentor, A Siemens Business. At Mentor, Raghav has co-created custom MBIST solution for various different memories. His focus is on memory testing, built in test technologies and DFT for automotive. Over last couple of years, he has been consulting efficient flow methodology for automotive ICs. He’s author of several IEEE paper and ITC posters. Raghav achieved his MS degree in VLSI system design from University of Southern California, United States.