10th IEEE INTERNATIONAL TEST CONFERENCE INDIA
2026
JULY 19-21, 2026 | RADISSON BLU, MARATHAHALLI, BENGALURU
POSTERS
Keyur Mahant and Mitulbhai Kansagara
Securing Design for Testability: Multi Layered Hardware Validation with Butterfly PUF
Venkatesh Kanago, Yashaswini Gadad and Sujithkumar Malaghan
A Process-Aware Multi-Task U-Net Framework for Mixed Wafer Defect Localisation and Diagnosis in Semiconductor Manufacturing
Sai Sumanth Muppavarapu and Christina Kichenamourty
Bluetooth BLE FW based Test Methodology on ATE
Hitesh Pradhan, Godithi Lakshmi Aruna Santhi, Rohit Mate, Sujit Panda and Vikas Gadi
Concurrent Functional Intelligence During Structural Test Using Selective Hierarchical Core Scan Bypass in Field-Deployable SLM IP
Govarthanam Krishnasamy
Leveraging Generative Artificial Intelligence for Automated Test Equipment (ATE) Test Program Generation in Semiconductor Validation and Production
Manoj Pachaiyan and Senthilkumar Dhamodharan
DRAC: A Dynamic Reconfigurable ATE Core for Extending Tester Capability in High-Resolution Data Converter Testing
Venkatraman Sivagnanam, Naveena Natarajan, Jaikrishnan Balakrishnan and Senthilkumar Dhamodharan
ATE-AMFE: Automated Multi-Platform Feasibility Engine
Jaya Surya Moorthy, Kalyana Sundaram Chandran and Senthilkumar Dhamodharan
Data-Driven Post-Silicon Validation Framework for High Bandwidth Memory in 2.5D Integration: Adaptive Stress Testing and Hierarchical Fault Isolation
Vistrita Tyagi, Kshitij Kulshreshtha, Amihay Rabenu and Manish Arora
Enabling Robust IEEE 1687 Interoperability in Heterogeneous IJTAG Networks through SIB Adaptor Architectures
V N Sivakumar Avvaru, Srinivasan Arulanandam and Harini Sriram
Virtual Emulation Ecosystem for Rapid Pre Silicon Validation
Sunny Kumar, Yeturi Om Sasankar and Philemon Daniel
A Shift-Left Framework for Automated RTL-Level Correction of Testability Violations to Improve Stuck-At and Transition Fault Coverage
Ashwani Kumar, Trupti Joshi, Vishal B Bhogade and Hemanthkumar Sivaraj
Smart Test Line Selection for Pre- and Post-Silicon Validation: Leveraging AI for Enhanced Efficiency
Tushar Jeevan, Chandan Kumar, Meetu Agarwal and Suraj Kashyap
Scalable Fanin-Fanout Analysis Using Precomputed Reconvergence Data for DFT Verification
Manish Mukul, Madhavan Srinivasan, Mahesh Salgaonkar and Aditya Gupta
A Cache‑Resident Linux Framework for System‑Level Validation on Enterprise‑Class Processors
Padmini Prakash and Pradip Kapure
HBM - Case study on a modern complex SOC with multi-die
Krunal Siddhapathak and Tathagat Biswas
A Weighted Hierarchical Approach to Testpoint Configuration driving Efficient and Optimized DFT Convergence
Ravi Bandla and Venkata Sreekanth Balijabudda
Protection of PUF Architectures Against Machine Learning Attacks Using Differential Privacy
Siddarth Ambhorkar, Vevekanenda Gonugunta, Ramesh Chandel, Gaurav Mattey, Daniel Tille, Aneri Jain, Naveen Kumar M, Nithin Radhakrishna Pillai and Aditya Girish
Detecting Crosstalk-Induced Static Noise Defects Using a Customized ATPG Test Flow
Meghana L, Sravan Kumar Challa, Leela Krishna Thota and Narendra Kumar Napa
Navigating the Intricacies of Clock Domain Crossing: The Role of Unified Power Format
Pervez Garg, Parth Kadiya and Pavithra K
A Novel Test Point Insertion Methodology for Enhanced Test Efficiency and Improved Design Quality
Salome Packiavathy, Venkatesh Vandrangi, Suraj Muzhayil Chathoth and Gevorg Torjyan
In System Test – Driven Memory Initialization for Improved Reliability in Multimode SoCs
Senthilkumar Dhamodharan, Sreeram V.R., Dyaneswaran Anguraj, Swetha Kumar and Shahana Balamurugan
An FPGA-Coordinated Validation Framework for Digital DUTs with DC and Protocol Testing for First Silicon Bring Up
Jai Sehgal, Aditi Bahuguna, Peeyush Bhatnagar, Sruthi Nanduru, Theo Toulas and Prakyath Madadi
Pattern Count Optimization and Test Cost Reduction Using TSO.ai for ATPG
Satyam Kuar and Jaynarayan T Tudu
A Functionally Self-Testable RISC-V Processor Using a Custom Test Instruction Set