10th IEEE INTERNATIONAL TEST CONFERENCE INDIA
2026
JULY 19-21, 2026 | RADISSON BLU, MARATHAHALLI, BENGALURU
POSTERS
Keyur Mahant and Mitulbhai Kansagara
Securing Design for Testability: Multi Layered Hardware Validation with Butterfly PUF
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Venkatesh Kanago, Yashaswini Gadad and Sujithkumar Malaghan
A Process-Aware Multi-Task U-Net Framework for Mixed Wafer Defect Localisation and Diagnosis in Semiconductor Manufacturing
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Sai Sumanth Muppavarapu and Christina Kichenamourty
Bluetooth BLE FW based Test Methodology on ATE
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Hitesh Pradhan, Godithi Lakshmi Aruna Santhi, Rohit Mate, Sujit Panda and Vikas Gadi
Concurrent Functional Intelligence During Structural Test Using Selective Hierarchical Core Scan Bypass in Field-Deployable SLM IP
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Govarthanam Krishnasamy
Leveraging Generative Artificial Intelligence for Automated Test Equipment (ATE) Test Program Generation in Semiconductor Validation and Production
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Manoj Pachaiyan and Senthilkumar Dhamodharan
DRAC: A Dynamic Reconfigurable ATE Core for Extending Tester Capability in High-Resolution Data Converter Testing
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Venkatraman Sivagnanam, Naveena Natarajan, Jaikrishnan Balakrishnan and Senthilkumar Dhamodharan
ATE-AMFE: Automated Multi-Platform Feasibility Engine
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Jaya Surya Moorthy, Kalyana Sundaram Chandran and Senthilkumar Dhamodharan
Data-Driven Post-Silicon Validation Framework for High Bandwidth Memory in 2.5D Integration: Adaptive Stress Testing and Hierarchical Fault Isolation
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Vistrita Tyagi, Kshitij Kulshreshtha, Amihay Rabenu and Manish Arora
Enabling Robust IEEE 1687 Interoperability in Heterogeneous IJTAG Networks through SIB Adaptor Architectures
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V N Sivakumar Avvaru, Srinivasan Arulanandam and Harini Sriram
Virtual Emulation Ecosystem for Rapid Pre Silicon Validation
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Sunny Kumar, Yeturi Om Sasankar and Philemon Daniel
A Shift-Left Framework for Automated RTL-Level Correction of Testability Violations to Improve Stuck-At and Transition Fault Coverage
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Ashwani Kumar, Trupti Joshi, Vishal B Bhogade and Hemanthkumar Sivaraj
Smart Test Line Selection for Pre- and Post-Silicon Validation: Leveraging AI for Enhanced Efficiency
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Tushar Jeevan, Chandan Kumar, Meetu Agarwal and Suraj Kashyap
Scalable Fanin-Fanout Analysis Using Precomputed Reconvergence Data for DFT Verification
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Manish Mukul, Madhavan Srinivasan, Mahesh Salgaonkar and Aditya Gupta
A Cache‑Resident Linux Framework for System‑Level Validation on Enterprise‑Class Processors
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Padmini Prakash and Pradip Kapure
HBM - Case study on a modern complex SOC with multi-die
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Krunal Siddhapathak and Tathagat Biswas
A Weighted Hierarchical Approach to Testpoint Configuration driving Efficient and Optimized DFT Convergence
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Ravi Bandla and Venkata Sreekanth Balijabudda
Protection of PUF Architectures Against Machine Learning Attacks Using Differential Privacy
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Siddarth Ambhorkar, Vevekanenda Gonugunta, Ramesh Chandel, Gaurav Mattey, Daniel Tille, Aneri Jain, Naveen Kumar M, Nithin Radhakrishna Pillai and Aditya Girish
Detecting Crosstalk-Induced Static Noise Defects Using a Customized ATPG Test Flow
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Meghana L, Sravan Kumar Challa, Leela Krishna Thota and Narendra Kumar Napa
Navigating the Intricacies of Clock Domain Crossing: The Role of Unified Power Format
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Pervez Garg, Parth Kadiya and Pavithra K
A Novel Test Point Insertion Methodology for Enhanced Test Efficiency and Improved Design Quality
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Salome Packiavathy, Venkatesh Vandrangi, Suraj Muzhayil Chathoth and Gevorg Torjyan
In System Test – Driven Memory Initialization for Improved Reliability in Multimode SoCs
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Senthilkumar Dhamodharan, Sreeram V.R., Dyaneswaran Anguraj, Swetha Kumar and Shahana Balamurugan
An FPGA-Coordinated Validation Framework for Digital DUTs with DC and Protocol Testing for First Silicon Bring Up
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Jai Sehgal, Aditi Bahuguna, Peeyush Bhatnagar, Sruthi Nanduru, Theo Toulas and Prakyath Madadi
Pattern Count Optimization and Test Cost Reduction Using TSO.ai for ATPG
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Satyam Kuar and Jaynarayan T Tudu
A Functionally Self-Testable RISC-V Processor Using a Custom Test Instruction Set
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