10^th IEEE INTERNATIONAL TEST CONFERENCE INDIA
2026

JULY 19-21, 2026 | RADISSON BLU, MARATHAHALLI, BENGALURU

DISTINGUISHED ADDRESSES

Don Chan

Cadence

From Point Tools to Agentic AI: How EDA has impacted Semiconductor Industry

Electronic Design Automation (EDA) has been the driving force behind decades of semiconductor innovation, enabling engineers to design increasingly complex chips while sustaining the pace of Moore's Law. As transistor scaling approaches its physical limits, the industry is transitioning toward heterogeneous chiplet-based architectures, 3D integration, and AI-driven design methodologies. This talk explores the evolution of EDA from traditional point tools to intelligent, agentic AI workflows, highlighting how advances in design technology co-optimization, DFT methodologies, and AI-assisted automation are reshaping semiconductor design. Attendees will gain insights into the next generation of EDA technologies that will power future innovations in high-performance computing and artificial intelligence.

Speaker Biography —Don Chan is Vice President of Research and Development at Cadence, where he leads the Foundry organization and drives strategic partnerships across the global semiconductor ecosystem. He oversees technology enablement, process certification, and customer support for advanced semiconductor nodes while also leading marketing and business development for Cadence's Digital and Signoff product portfolio. Throughout his career, he has led key R&D initiatives spanning 3D-IC, Conformal, Modus, and Stratus technologies, and previously held leadership positions at Synopsys and Fujitsu Micro.

His extensive experience in semiconductor design enablement, foundry collaboration, and advanced EDA technologies has provided him with a unique perspective on the evolution of chip design methodologies. By working closely with foundries, customers, and global R&D teams to deliver next-generation design solutions, Don is uniquely positioned to discuss how agentic AI, heterogeneous integration, and intelligent EDA workflows are transforming the future of semiconductor design.

Alpa Sood

Teradyne

The Critical Role of Test Strategy in India's Semiconductor Growth

As India accelerates its ambitions of becoming a global semiconductor hub, developing a robust test ecosystem is emerging as a strategic priority. Advanced test methodologies are essential not only for ensuring product quality and reliability but also for strengthening manufacturing capabilities, enabling supply chain resilience, and enhancing global competitiveness. This talk explores the pivotal role of test strategy in building a sustainable semiconductor ecosystem, highlighting the importance of collaboration between industry, government, and academia to support India's vision of becoming a leading semiconductor nation.

Speaker Biography —Alpa is Country Manager for India at Teradyne, bringing over 15 years of experience across business, policy, and government affairs. Throughout her career, she has worked closely with the Government of India and various state governments to foster the growth and innovation of the semiconductor ecosystem, building strong partnerships between the public and private sectors that create opportunities for businesses, entrepreneurs, and the broader industry.

Prior to joining Teradyne, Alpa led government affairs, legal, and strategic policy engagement at Marvell India, where she developed deep expertise in navigating complex industry landscapes. Her extensive background in bridging public and private sector relationships makes her a driving force in shaping India's semiconductor future.

Rajesh Vaddempudi

Advantest, India

The Intelligent Silicon Era: Redefining Semiconductor Test Through Innovation, AI, and Collaboration

More details coming soon

Arojit Roychowdhury

Qualcomm