10th IEEE INTERNATIONAL TEST CONFERENCE INDIA
2026
JULY 19-21, 2026 | RADISSON BLU, MARATHAHALLI, BENGALURU
PROGRAM AGENDA
PROGRAM AGENDA
Day 0
Tutorials & Industry Test Challenge
Sunday, July 19, 2026
08:00 AM – 09:15 AM
Registrations
09:15 AM – 10:45 AM
Grand Victoria 1
CHAIRBharath Nandakumar
Squeezing Quality into Cents: DFT Strategies for Low-cost MCUs
Tutorial Track 1(a)
Vishal Diwan and Mudasir Kawoosa (Texas Instruments)
Grand Victoria 2
CHAIRRajit Karmakar
LLM for VLSI Design, Automation and Test
Tutorial Track 2(a)
Chandan Karfa (IIT Guwahati)
Arabica & Robusta
CHAIRRama Sireesha Arisetti
Mission Mode Scan Dump Using IJTAG and TAP Customization: Architecture, Implementation, and Practical Considerations
Tutorial Track 3(a)
Sreekanth G Pai and Raseena KA (Marvell)
Brain Box
CHAIRAbhishek Chaudhary
Testing Chiplet-Based 2.5D/3D ICs : An Academia/Industry perspective
Tutorial Track 4(a)
Binod Kumar, Manisha Kumari (IIT Jodhpur), Jaynarayan T Tudu (IIT Tirupati), Jyotirmoy Saikia and Sagar Kumar (Cadence)
10:45 AM – 11:15 AM
Tea/Coffee Break
11:15 AM – 12:45 PM
Grand Victoria 1
CHAIRBharath Nandakumar
Closed Loop Test Engineering – From Design to Mass Production
Maheedhar Jalasutram, Jeren Ku and Daejin Shin (Google)
Grand Victoria 2
CHAIRRajit Karmakar
Machine Learning is Inevitable or Not: A DFT Designer’s View
Ankush Srivastava (Qualcomm)
Arabica & Robusta
CHAIRRama Sireesha Arisetti
Beyond Scan Dump: Why IEEE P2929 Enables True Scan State Extraction
Andy Hughes (Siemens EDA)
Brain Box
CHAIRAbhishek Chaudhary
Testing Chiplet-Based 2.5D/3D ICs : An Academia/Industry perspective
Binod Kumar, Manisha Kumari (IIT Jodhpur), Jaynarayan T Tudu (IIT Tirupati), Jyotirmoy Saikia and Sagar Kumar (Cadence)
12:45 PM – 01:45 PM
Lunch Break
01:45 PM – 03:15 PM
Grand Victoria 1
CHAIRBharath Nandakumar
Testing to Self Testing: Self Test Driven Functional Safety for ISO 26262 Compliant Automotive SoCs
Tutorial Track 1(b)
Rajesh Kumar Tiwari and Mohammed Zuber P Malek (Qualcomm)
Grand Victoria 2
CHAIRRajit Karmakar
The Seamless Integration of Packetized Scan and In-system test with Advanced ATE Equipment
Tutorial Track 2(b)
Hagen Goller (Advantest)
Arabica & Robusta
CHAIRRama Sireesha Arisetti
Advanced Test Data Analytics for Yield and Quality Improvement
Tutorial Track 3(b)
Navya Rastogi, Shamitha Rao, Shrestha Hota (Synopsys)
Brain Box
CHAIRAbhishek Chaudhary
Industry Test Challenge
invite only session
Talk1
Talk2
Break
Talk3
Talk4
Break
Panel Discussion
Correlation Crisis in Semiconductor Test: Can AI Bridge the Gap? Moderator: Sameer Chillarige (Cadence) | Panelists: Udayakiran Yallamaraju (Qualcomm), John Schulze (AMD), C Jagadish Kumar (Intel), Raghu G G (Infineon)
03:15 PM – 03:45 PM
Tea/Coffee Break
Brain Box
CHAIRAbhishek Chaudhary
Industry Test Challenge
invite only session
Talk1
Talk2
Break
Talk3
Talk4
Break
Panel Discussion
Correlation Crisis in Semiconductor Test: Can AI Bridge the Gap? Moderator: Sameer Chillarige (Cadence) | Panelists: Udayakiran Yallamaraju (Qualcomm), John Schulze (AMD), C Jagadish Kumar (Intel), Raghu G G (Infineon)
03:45 PM – 05:15 PM
Grand Victoria 1
CHAIRBharath Nandakumar
Understanding Test Escapes and the Limitations of Scan DFT Testing
Adit Singh (Auburn university)
Grand Victoria 2
CHAIRRajit Karmakar
Scalable ATE Hardware Design: From Concept to Manufacturing with Reusable Architecture
Lokapriya B, Senthilkumar Dhamodharan and Dyaneswaran Anguraj (Caliber Interconnects)
Arabica & Robusta
CHAIRRama Sireesha Arisetti
Customer Centric Post Silicon Validation Approach for System on Chip (SoC)
Ravishankar Manishankar and Siloni Palani (Intel)
Brain Box
CHAIRAbhishek Chaudhary
Industry Test Challenge
invite only session
Talk1
Talk2
Break
Talk3
Talk4
Break
Panel Discussion
Correlation Crisis in Semiconductor Test: Can AI Bridge the Gap? Moderator: Sameer Chillarige (Cadence) | Panelists: Udayakiran Yallamaraju (Qualcomm), John Schulze (AMD), C Jagadish Kumar (Intel), Raghu G G (Infineon)
06:30 PM – 07:45 PM
Arabica & Robusta