10th IEEE INTERNATIONAL TEST CONFERENCE INDIA
2026
JULY 19-21, 2026 | RADISSON BLU, MARATHAHALLI, BENGALURU
PROGRAM AGENDA
Day 0
Tutorials & Industry Test Challenge
Sunday, July 19, 2026
| TIME | TRACK 1 (A)Grand Victoria 1 | TRACK 2 (A)Grand Victoria 2 | TRACK 3 (A)Arabica & Robusta | TRACK 4Brain Box |
|---|---|---|---|---|
08:00 AM – 09:15 AM | Registrations | |||
09:15 AM –10:45 AM | Squeezing Quality into Cents: DFT Strategies for Low-cost MCUsVishal Diwan and Mudasir Kawoosa (Texas Instruments) | LLM for VLSI Design, Automation and TestChandan Karfa (IIT Guwahati) | Mission Mode Scan Dump Using IJTAG and TAP Customization: Architecture, Implementation, and Practical ConsiderationsSreekanth G Pai and Raseena KA (Marvell) | Testing Chiplet-Based 2.5D/3D ICs : An Academia/Industry perspectiveBinod Kumar, Manisha Kumari (IIT Jodhpur), Jaynarayan T Tudu (IIT Tirupati), Jyotirmoy Saikia and Sagar Kumar (Cadence) |
10:45 AM – 11:15 AM | Tea/Coffee Break | |||
11:15 AM –12:45 PM | Closed Loop Test Engineering - From Design to Mass ProductionMaheedhar Jalasutram (Google) | Machine Learning is Inevitable or Not: A DFT Designer’s ViewAnkush Srivastava (Qualcomm) | Beyond Scan Dump: Why IEEE P2929 Enables True Scan State ExtractionLee Harrison, Andy Hughes and Peter Orlando (Siemens EDA) | Testing Chiplet-Based 2.5D/3D ICs : An Academia/Industry perspectiveBinod Kumar, Manisha Kumari (IIT Jodhpur), Jaynarayan T Tudu (IIT Tirupati), Jyotirmoy Saikia and Sagar Kumar (Cadence) |
12:45 PM – 01:45 PM | Lunch Break | |||
01:45 PM –03:15 PM | Testing to Self Testing: Self Test Driven Functional Safety for ISO 26262 Compliant Automotive SoCsRajesh Kumar Tiwari and Mohammed Zuber P Malek (Qualcomm) | The Seamless Integration of Packetized scan and In-system test with Advanced ATE EquipmentLee Harrison (Siemens EDA) | Advanced Test Data Analytics for Yield and Quality ImprovementNavya Rastogi, Shamitha Rao, Shrestha Hota (Synopsys) and Soumya Mittal (Qualcomm) | No Activity Planned |
03:15 PM – 03:45 PM | Tea/Coffee Break | |||
03:45 PM –05:15 PM | Understanding Test Escapes and the Limitations of Scan DFT TestingAdit Singh (Auburn university) | Scalable ATE Hardware Design: From Concept to Manufacturing with Reusable ArchitectureLokapriya B, Senthilkumar Dhamodharan and Vaishnavi Saravanan (Caliber Interconnects) | Customer Centric Post Silicon Validation Approach for System on Chip (SoC)Ravishankar Manishankar and Siloni Pilani (Intel) | No Activity Planned |
05:15 PM –06:15 PM | No Activity Planned | |||
06:30 PM –07:45 PM | No Activity Planned | TTTC Workshop | No Activity Planned | |