10^th IEEE INTERNATIONAL TEST CONFERENCE INDIA
2026

The rapid evolution of semiconductor technologies, including AI accelerators, chiplet architectures, high-speed interfaces, and advanced packaging, requires innovative test engineering solutions to ensure product quality, reliability, and reduced time-to-market. This presentation highlights a research-driven approach to semiconductor test engineering that integrates Automatic Test Equipment (ATE), advanced test hardware, package design, signal and power integrity analysis, and AI-assisted automation across the silicon development lifecycle. It presents a portfolio of research covering production test optimization, post-silicon validation, intelligent fault diagnosis, scan optimization, reliability assessment, and emerging methodologies for photonics, neuromorphic, quantum, and heterogeneous semiconductor devices. The presentation also demonstrates how reusable hardware architectures, predictive analytics, and design automation enhance testing efficiency and manufacturing readiness. By combining industrial engineering expertise with applied research, the proposed framework establishes semiconductor test engineering as a key enabler of silicon innovation, delivering scalable, reliable, and cost-effective solutions for next-generation integrated circuits and advanced electronic systems.

This presentation shows how Teradyne's solutions cover the full electronics manufacturing value chain, wafer to rack, from chip level testing through packaging, memory, board level, and system level test, to fully assembled AI data center infrastructure. It highlights the growing importance of system level test in catching real world defects that traditional test methods can miss, particularly for complex, multi die AI and compute chips. It also covers Teradyne's robotics business as a complementary growth area, supporting automation across manufacturing and logistics operations.

As performance-driven digital designs continue to scale in complexity, Design-for-Test (DFT) engineering faces increasing pressure to validate test content rapidly and with high confidence. While DFT structures and patterns are defined pre-silicon, effective validation and debug are typically deferred to post-silicon environments, often relying on internally developed benches with limited observability and inconsistent alignment to downstream ATE requirements. At the same time, growing pattern volumes and increasingly complex scan architectures expose the limitations of ad hoc validation approaches, leading to inefficiencies and late-stage rework. This work introduces a structured methodology for post-silicon DFT validation, spanning controlled execution of test content, iterative debug and refinement, systematic margin exploration, and readiness preparation for production test. By emphasizing execution fidelity, observability, and workflow consistency, the approach enables earlier insight into test behavior, reduces debug cycles, and improves confidence ahead of ATE deployment. Overall, this methodology-driven validation provides a more predictable and scalable path to test readiness, supporting the demands of advanced digital designs.

Over the past decades, scan and BIST patterns have typically been treated as a black box by most test engineers. These patterns were executed, results were retrieved and logged, and optionally, additional failure data was recorded for diagnosis and yield learning. The abundance of replicated units with spares is changing this approach. The SSN On-Chip Compare feature enables the testing of an unlimited number of units in parallel with a constant size pattern and efficiently identifies defective units that must be replaced by spares. To utilize features like on-chip compare or per-core Pass/Fail detection, semantic information about the content of the pattern is required. Specific bits of the patterns must be read or modified during test program execution. In the past, this has been achieved by adding semantic information to STIL annotations, which are converted to external csv files or pattern comments and parsed by user code. Tessent Shell and SmarTest introduce new capabilities that establish a solid foundation for handling the SSN metadata and enable convenient and efficient access to it at both the API level and in user interfaces for interactive usage and debugging. This paper explains these new capabilities and demonstrates how an end-to-end solution, including pattern translation tools, works.