10th IEEE INTERNATIONAL TEST CONFERENCE INDIA
2026
JULY 19-21, 2026 | RADISSON BLU, MARATHAHALLI, BENGALURU
KEYNOTE SPEAKERS
Yervant Zorian
Synopsys
Designing Chiplets and 3DIC for Quality and Reliability
As semiconductor innovation moves beyond traditional transistor scaling, chiplet-based architectures and 3D integrated circuits are emerging as the foundation of next-generation computing systems. While these technologies enable unprecedented levels of performance, scalability, and heterogeneous integration, they also introduce new challenges in test, quality, reliability, and lifecycle management. This keynote explores the design methodologies, DFT strategies, and reliability frameworks required to ensure robust, high-quality chiplet and 3DIC systems, highlighting the critical role of advanced test technologies in enabling the future of semiconductor integration.
Speaker Biography —Dr. Yervant Zorian is President of Synopsys Armenia, Chief Architect and Fellow at Synopsys, and one of the world's foremost pioneers in semiconductor test, Built-In Self-Test (BIST), Design-for-Test (DFT), and Electronic Design Automation (EDA). Over a distinguished career spanning industry, academia, and standards development, he has held leadership positions at Synopsys, Virage Logic, LogicVision, and AT&T Bell Laboratories. He currently serves as President of the IEEE Test Technology Technical Council (TTTC) and founded the IEEE 1500 Standardization Working Group.
A pioneer of modern BIST methodologies, Dr. Zorian has fundamentally shaped semiconductor test architectures and international DFT standards through more than 40 U.S. patents, four books, and over 350 technical publications. A recipient of numerous prestigious honors, including the IEEE Industrial Pioneer Award for his contributions to BIST and the IEEE TTTC Lifetime Contribution Award, he continues to be a leading voice driving innovation in semiconductor test, reliability, and advanced system integration.
Subhashish Mitra
Stanford University
Silent Data Corruption by 10× Test Escapes Threatens Reliable Computing
Today's test and reliability practices cannot meet the levels of thoroughness demanded by today's (and future) systems, from (autonomous) cars to the cloud. Too many defective compute chips escape existing manufacturing tests – at least an order of magnitude more than industry targets across compute chip types deployed in data centers. Several hyperscalers have recently reported alarming system-level effects, such as Silent Data Corruptions (SDCs), caused by test escapes. Left unaddressed, these SDCs pose a major threat to reliable computing. Business-as-usual approaches, including cell-aware test patterns and existing system-level testing, are inadequate. Future architectures, from chiplets to 3D, create even bigger challenges. These create golden opportunities for new "System-Driven" approaches – from extremely thorough testing, deemed impossible today, all the way to cost-effective tolerance and prediction of failures in hardware during system operation.
Speaker Biography —Subhashish Mitra is the William E. Ayer Endowed Chair Professor at Stanford University and a globally recognized leader in robust computing, system reliability, and electronic design automation. Over decades of pioneering research, his innovations in testing, validation, fault prediction, and resilience have shaped modern semiconductor systems and influenced technologies deployed across cloud, AI, and automotive platforms worldwide.
His extensive work with academia, industry, and national semiconductor initiatives has provided him with unique insights into the reliability challenges facing next-generation computing systems, making him a leading voice on the future of trustworthy and resilient computing.
Senthilkumar Dhamodharan
Caliber Interconnects
SI Complexity to AI Revolution: India’s Silicon Leap 2047
As artificial intelligence redefines the semiconductor landscape, intelligent testing, validation, and manufacturing have become essential enablers of innovation. This keynote explores how AI-driven methodologies, digital twins, and ecosystem collaboration can accelerate India’s semiconductor journey and strengthen its position in the global technology value chain.
Speaker Biography —Senthilkumar Dhamodharan is Vice-President of Semiconductor Test Engineering at Caliber, where he leads the Test Engineering Division responsible for validating SoC, PMIC, Digital, Mixed-Signal, and RF products across ATE and bench platforms. With over 19 years of experience at industry leaders including Qualcomm, AMD, and NXP, he has built deep expertise in semiconductor test, physical design, DFT, and high-volume manufacturing. He also drives strategic initiatives in intellectual property development and leads a high-performance engineering organization of more than 250 test engineers. He holds a Master's degree in VLSI Design from Anna University.
Drawing on extensive leadership across semiconductor validation, manufacturing test, and engineering strategy, Senthil has played a pivotal role in advancing innovative test methodologies for complex silicon products. His experience in building scalable engineering organizations and driving next-generation test solutions provides him with valuable insights into the evolving landscape of semiconductor testing and intelligent silicon.
Jeff Rearick
AMD
AI in Test: Fear It or Harness It
Artificial Intelligence is rapidly transforming industries worldwide, creating both unprecedented opportunities and significant challenges. In the semiconductor test ecosystem, AI is reshaping how products are designed, validated, and tested, while simultaneously introducing new requirements for ensuring the reliability and trustworthiness of AI-driven systems. This keynote examines the evolving relationship between AI and test, highlighting how the test community plays a critical role in enabling the next generation of intelligent technologies.
Speaker Biography —Jeff Rearick is a Senior Fellow at AMD where he has led the DFX Strategy team for the past 19 years, after spending the previous 22 years at HP and Agilent Technologies working on DFT and test methodologies. He holds 50 patents, has published many technical papers, serves on the ITC Steering Committee, and remains deeply engaged in IEEE working groups, including serving as the Editor for all three of the IEEE 1687 family of standards currently in flight.
Jeff's day job of looking just far enough into the future of test and debug and validation to keep a steady stream of innovations coming down the pipeline to intercept ever-advancing AMD products keeps him at the forefront of emerging trends, including the epochal disruption that AI has brought to our field.
Nilanjan Mukherjee
Siemens
Built-in Intelligence – Leveraging Advanced DFT for Silicon Health Monitoring
As semiconductor technologies continue to evolve, ensuring silicon quality, reliability, and long-term health has become increasingly challenging. Modern designs require test methodologies that extend beyond manufacturing to enable continuous monitoring throughout the product lifecycle. This talk explores how advanced Design-for-Test (DFT) infrastructures provide the foundation for comprehensive silicon health monitoring, integrating on-chip intelligence, diagnostics, and lifecycle analytics to improve test quality, reduce cost, and enhance reliability from manufacturing through field deployment.
Speaker Biography —Nilanjan Mukherjee is Vice President of Software Engineering for Tessent Silicon Lifecycle Solutions at Siemens EDA, where he leads the development of advanced technologies spanning the complete silicon lifecycle, from design through field operation. A globally recognized expert in semiconductor test and diagnostics, he has pioneered innovations in test compression, Logic BIST, Memory BIST, low-power DFT, in-field testing, and silicon lifecycle management. His contributions include foundational work on EDT/TestKompress, VersaPoint Test Points, Observation Scan Technology, low-power hybrid EDT/Logic BIST, and packetized scan-based in-field testing.
His work has significantly advanced the industry's approach to DFT, silicon diagnostics, and predictive health monitoring through the integration of on-chip sensing and data analytics. Holding over 60 U.S. patents, authoring more than 100 technical publications, and receiving numerous prestigious awards, including the IEEE Donald O. Pederson Outstanding Paper Award, the ITC Most Significant Paper Award, and multiple Best Paper Awards, Nilanjan continues to be a leading voice shaping the future of intelligent test and silicon lifecycle management.
Bizhan Delgoshaei
From Silent Patient to Self-Healing Silicon: The Four Evolutionary Stages of DFT in Mass Production
As semiconductor devices grow in complexity and production volumes continue to scale, ensuring silicon quality and reliability has become increasingly challenging. This keynote explores the evolution of Design for Testability (DFT) from a traditional diagnostic tool into an intelligent, lifecycle-driven framework that enables improved yield, reliability, and manufacturing efficiency. By examining the four evolutionary stages of DFT, it highlights how modern test methodologies are shaping the future of autonomous and self-healing silicon.
Speaker Biography —Bizhan Delgoshaei is Director of Custom Silicon Engineering Operations at Google, where he oversees Tensor manufacturing, test, and quality. Over more than two decades, he has led the successful ramp of advanced semiconductor products, including FPGAs, SoCs, memory, PMICs, and security devices: from development to high-volume production.
Through leadership roles at Google, Apple, and Altera, he has gained deep expertise in silicon manufacturing, quality engineering, and operational excellence. His extensive industry experience provides him with valuable insights into the evolving role of Design for Testability (DFT) in enabling reliable, scalable, and increasingly intelligent semiconductor systems.