10th IEEE INTERNATIONAL TEST CONFERENCE INDIA
2026
JULY 19-21, 2026 | RADISSON BLU, MARATHAHALLI, BENGALURU
INDUSTRY SESSIONS
Jayashree Saxena
Anora Labs
A Day in the Life of a DFT Engineer - Can Agents Help?
Concepts such as scan and BIST have been routinely used in the industry for many decades. Nonetheless, the complexity of Design for Test (DFT) implementation continues to challenge us every day. This talk will provide a DFT Engineer’s view of the challenges and will highlight the exacting attention to detail required to implement DFT. In addition, the domain knowledge required to enable seamless integration with other parts of the design flow is a skill that is acquired over many years. While automation has made significant inroads to ease several of these challenges, there is still a lot that rests on individual skills and attention. Can we harness AI agents judiciously to understand the nuances of DFT implementation and help where the impact will be felt the most ?
Speaker Biography —Jayashree Saxena has over 30 years of experience in Design-for-test. She currently holds the title of Vice President, Semiconductor DFT at Anora LLC. Prior to joining Anora in 2013, Jayashree spent close to 20 years at Texas Instruments. Jayashree holds a Master of Engineering in Electrical Communication Engineering from the Indian Institute of Science, Bangalore and a Ph.D in Electrical and Computer Engineering from the University of Massachusetts at Amherst.
Nithin Gopinath
Texas Instruments
Built-in Intelligence in Analog-to-Digital Convertors
As modern semiconductor systems demand higher speeds, greater integration, and lower power consumption, ensuring consistent analog performance has become increasingly challenging. This keynote explores the evolution of high-speed ADC testing, from traditional trimming techniques to intelligent digital-assisted correction and real-time background calibration. It highlights how built-in intelligence is transforming analog design and test methodologies, enabling improved performance, reduced test costs, and greater resilience to process, voltage, and temperature variations.
Speaker Biography —Nithin Gopinath is a Senior Member Technical Staff at Texas Instruments, where he has spent over 15 years advancing high-speed data converter technologies. His work in architecting, validating, and optimizing state-of-the-art ADC solutions has contributed to innovations in calibration techniques, performance optimization, and test efficiency across demanding applications including wireless communications, aerospace, defense, and instrumentation.
As Post-Silicon Validation & Test Manager for the High-Speed ADC group, Nithin has developed deep expertise in addressing the challenges of analog performance variability, test cost, and design complexity. His extensive experience with high-speed pipelined ADCs, sigma-delta ADCs, and intelligent calibration methodologies provides him with unique insights into the growing role of built-in intelligence in enabling robust, high-performance analog systems.
Nikhil Sudhakaran
Marvell
System Level Test at Hyperscale: Transforming DFT for Data Infrastructure
The rise of AI-driven data infrastructure is redefining the demands placed on modern semiconductor systems. As designs evolve from monolithic SoCs to heterogeneous, chiplet-based architectures featuring advanced packaging, high-bandwidth interfaces, and memory-centric computing, traditional Design-for-Test (DFT) approaches are no longer sufficient. This keynote explores how hyperscale workloads and platform-level integration are driving a shift toward system-level test strategies, highlighting the need for hierarchical, package-aware, and data-driven methodologies to ensure quality, reliability, and scalability in next-generation AI infrastructure.
Speaker Biography —Nikhil is an engineering leader with over two decades of experience in semiconductor design and test, currently serving as Director of Engineering at Marvell, where he leads Design-for-Test initiatives for custom silicon powering next-generation AI infrastructure in hyperscale data centers. Throughout his career at Marvell, Intel, and Qualcomm, he has played a pivotal role in delivering complex SoCs across client, server, mobile, IoT, and automotive markets.
His expertise spans the entire silicon lifecycle, from DFT architecture and verification to post-silicon validation, test development, and ATE bring-up. With deep experience in advanced test methodologies, multi-die systems, and high-performance computing platforms, Nikhil brings valuable insights into how Design-for-Test is evolving to address the challenges of hyperscale AI infrastructure and system-level integration.
Gopikrishna Siddula
SanDisk
Testing High-Speed NAND Flash Interface I/Os for Silicon Quality and Production Readiness.
This talk shares an industry perspective on testing high-speed flash interface I/Os for NAND flash-based storage systems, covering validation, signal integrity, margin assessment, silicon debug, and production screening to improve silicon quality and production readiness.
Speaker Biography —Gopikrishna Siddula has been a member of the Mixed-Signal IP team at SanDisk for over 12 years, specializing in the design and integration of high-performance memory interface I/Os. He holds an M.S. from IIIT Hyderabad and is an inventor on multiple U.S. patents covering high-speed I/O design, ESD protection, and memory interface technologies.
Through years of developing and integrating advanced memory interfaces, Gopikrishna has gained deep expertise in the challenges of achieving reliable, high-speed data communication. His experience in high-performance I/O design and innovation provides valuable insights into the testing methodologies required to ensure robust and efficient flash memory interfaces.
Anand Muthaiah
Tessolve
On-Chip Intelligence Transforming IC Testing
As integrated circuits become increasingly complex, traditional testing approaches are evolving toward intelligent, self-aware methodologies that enhance quality, reliability, and manufacturing efficiency. On-chip intelligence is enabling advanced capabilities such as real-time diagnostics, adaptive testing, built-in self-test, silicon health monitoring, and AI-assisted analytics, transforming test from a manufacturing checkpoint into a continuous lifecycle function. This talk explores how embedded intelligence is redefining IC testing, enabling faster validation, lower test costs, improved yield, and more resilient semiconductor systems across advanced packaging, chiplet architectures, and next-generation devices.
Speaker Biography —Anand Muthaiah is Senior Vice President and Head of the COE and Post Silicon Business Unit at Tessolve, bringing over 30 years of experience in semiconductor test, hardware, and package design. An expert in digital, analog, and mixed-signal testing, he has built extensive expertise in high-volume manufacturing, post-silicon validation, and advanced semiconductor engineering. At Tessolve, he leads strategic initiatives in advanced packaging, chiplet-based device testing, silicon validation, system-level test (SLT), photonics, and AI-driven manufacturing solutions. He holds an M.S. in Electrical Engineering from the University of South Florida and has held key technical and leadership roles at Cyrix Semiconductor, LTX Corporation, Intel Technologies, and Tessolve.
His broad experience across semiconductor design, validation, packaging, and manufacturing enables him to bridge emerging technologies with production-ready solutions. By driving innovations in chiplet testing, AI-assisted manufacturing workflows, and advanced validation methodologies, Anand brings a forward-looking perspective on improving efficiency, quality, and scalability across the semiconductor lifecycle.