Panel Discussion 1

Title: “The Conundrum of Low Power Testing: Challenges, Solutions, and Associated Cost“

Abstract: The significant growth of the wireless and portable devices is driving deployment of sophisticated power reduction techniques in the mission mode. At the same time, shrinking technology nodes and demand for high quality are mandating use of advanced fault models, resulting in massive test data volume. Moreover, compact test pattern sets cause maximum toggle activities and hence not suitable for low power testing. To keep test time under control, techniques such as testing multiple cores together or increasing frequency of test clocks are deployed. All these measures increase test power consumption and cause yield loss. To circumvent yield loss issue, commonly used measures are voltage boost, low toggle ATPG patterns or serialized core testing. The panel will discuss low power testing challenges, available solutions, and associated cost.

  1. What are the low power test challenges?
  2. What are the various techniques used to contain power during Logic Testing?
  3. What are the various techniques used to contain power during Memory testing?
  4. Do we have good pre silicon test power estimation tools and processes?
  5. How to account for glitch power?
  6. Thoughts on impacts of global IR drop and local IR drop.
  7. Do we need to be concerned about L di/dt?
  8. Is applying voltage boost a correct strategy to improve yield and reduce test time?
  9. Does voltage boost mask effects of some real defects?
  10. Thoughts on testing low power instruments like power switches, isolation cells etc.
  11. Thoughts on future measures to address low power testing issues.            

Panelists:

  1. Rubin Parekhji (TI)
  2. Adit Singh (Auburn)
  3. Nilanjan Mukherjee (Siemens)
  4. Gaurav Bhargava (Qualcomm)
  5. Parthajit Bhattacharya (Synopsys)

Moderator: Kamlesh Pandey (Qualcomm)

Panelists Details:

1. Rubin Parekhji

Rubin Parekhji (TI)

Rubin Parekhji has been with Texas Instruments (India), Bangalore, since 1996, where he has led and mentored DFT teams on various IP / SOC design and test technology projects across multiple groups, resulting in many DFT and test innovations, and adoption of new test technologies across TI teams world-wide. He has co-authored more than 70 peer reviewed technical papers and has contributed to more than 20 tutorials and special sessions in leading international conferences. He has played chair roles in IEEE conferences and standards. He has been a visiting faculty member at IIT Bombay and IISc Bangalore, has guided a large number of students on industrial projects, and is an active liaison for several TI sponsored SRC projects. He is the joint inventor of 25 granted patents and is a distinguished member of technical staff at TI. He has a Ph.D. from Indian Institute of Technology, Bombay, India.

2. Adit Singh

Adit Singh (Auburn)

Adit Deva Singh is Godbold Endowed Chair Professor of Electrical and Computer Engineering at Auburn University, where he has served on the faculty since 1991. Earlier he has held faculty positions at the University of Massachusetts and Virginia Tech, in Blacksburg, and visiting professorships at the University of Freiburg, Germany, and the University of Tokyo, Japan. His research interests span all aspects of VLSI technology, with an emphasis on IC test and reliability. Professor Singh has held leadership roles as General Chair/Co-Chair/Program Chair for dozens of VLSI design and test conferences, including on the steering committee of ITC. He helped co-found the International Conference of VLSI Design in India in 1990-91. For two terms (2007-11), he was Chair of the IEEE Test Technology Technical Council (TTTC), and also served (2011-2015) on the Board of Governors of the IEEE Council on Design Automation (CEDA). He holds a B.Tech in Electrical Engineering from IIT Kanpur, and the M.S. and Ph.D. from Virginia Tech. He is a Life Fellow of IEEE.

3. Nilanjan Mukherjee

Nilanjan Mukherjee (Siemens)

Nilanjan Mukherjee is a Senior Director of Engineering for Tessent Silicon Lifecyle Solutions at Siemens EDA. He has been actively involved in the R&D of key technologies in the areas of test quality, test compression, Logic BIST, Memory BIST, low power DFT, and diagnosis. Some of his major accomplishments include being a co-inventor and an architect of EDT/TestKompress, the VersaPoint Test Points technology, a Low Power Hybrid EDT/Logic BIST scheme for automotive ICs, and the Observation Scan Technology (LBIST-OST). Currently, his focus is on developing new test solutions for automotive and data-center markets.

Nilanjan has co-authored more than 85 technical papers and is a co-inventor of 55 US patents. He has received numerous awards including Best Paper Awards at VTS 2020, VLSI Design 2009, ATS 2001, and VTS 1995, the Most Significant Paper Award at ITC 2012, Siemens DISW Invention of the year 2019, and the Donald O. Pederson Outstanding Paper Award in 2006.

Nilanjan received a B.Tech. (Hons) degree from IIT, Kharagpur, and a Ph.D. degree from McGill University, Canada. He has given numerous tutorials, short-term courses, and invited talks at premier IEEE/ACM conferences, symposia, universities, and companies across the world.

4. Gaurav Bhargava

Gaurav Bhargava (Qualcomm)

Gaurav Bhargava is a Sr. Director, Technology at Qualcomm India Pvt Ltd. He is responsible for DFT Test Productization in High Volume Manufacturing for Qualcomm’s Snapdragon product lines. In his 20-year career with Qualcomm (USA & India), Gaurav has contributed within various fields of Test – ranging from Pre-Silicon Test Architectures, DFT Implementation & Fault Modelling to Post-Silicon Test Development & Product/Test Engineering. He has seen SoC Designs & Semiconductor Test evolve from the early 130nm era to the current 3nm where he actively contributes towards Yield, Quality, Reliability & Test-Cost Goals across product lines. He holds multiple patents in DFT and has published several papers in leading Semiconductor Test Conferences globally. Gaurav earned his bachelor’s degree in Electronics Engineering from University of Mumbai and holds a master’s degree in Computer Science & Engineering from State University of New York, Buffalo, USA.

5. Parthajit Bhattacharya

Parthajit Bhattacharya (Synopsys)

Parthajit Bhattacharya is a Director R&D, at Synopsys. Working with Synopsys since 2008, leading a team of excellent engineers who are developing cutting edge technologies in TestMAX family of products. Collaborating with esteemed customers on various aspects of DFT and ATPG, addressing critical test issues and enabling effective test for the most demanding applications. Interested in learning and collaborating on new technology for solving current and future challenges in VLSI Test.

Moderator Details:

Kamlesh Pandey

Kamlesh Pandey (Qualcomm)

Kamlesh Pandey is a Director, Engineer at Qualcomm India Pvt Ltd. He joined Qualcomm Bangalore in 2021. He is currently leading ATPG vertical of BDC DFT group. Prior to joining Qualcomm, he has worked at Broadcom India Pvt Ltd for 17 years and his last designation at Broadcom was Distinguished Engineer. At Broadcom he led a team working on DFT architecture, DFT flow development, DFT implementation on SOCs, ATE bringup and production support for Settop box and DOCSIS SOCs. Prior to joining Broadcom, he was DFT engineer at Cisco Systems. His contribution in the field of research includes multiple US patents and invention of Broadcom in-house at-speed logic test architecture known as CTSA. He has received M.Tech. in Microelectronic and VLSI systems from Indian Institute of Technology Kanpur.

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Address: 90/4 Outer Ring Road, Marathahalli, Bengaluru, 560037, India

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