Invited Talks

Invited Talk 1: Special Session on Security

Speaker:

Ujjwal Guin, Auburn University

Title: “Recent Advancement in Detecting Recycled ICs

Bio: 
Ujjwal Guin is currently an Assistant Professor at the Department of Electrical and Computer Engineering, Auburn University. He received his Ph.D.degree from the University of Connecticut in 2016. He is actively involved in projects in the field of Hardware Security and Trust, Supply Chain Security, Cybersecurity, and VLSI Design and Test. He has developed several on-chip structures and techniques to improve the security, trustworthiness, and reliability of integrated circuits. His current research interests include Hardware Security & Trust, Blockchain, Supply Chain Security, Cybersecurity, and VLSI Design & Test. He is a co-author of the book ”Counterfeit Integrated Circuits: Detection and Avoidance”. He has authored several journal articles and refereed conference papers. His projects are sponsored by the National Science Foundation (NSF), Air Force Research Laboratory (AFRL), and Auburn University.

Prof. Guin was actively involved in developing a web-based tool, Counterfeit Defect Coverage Tool (CDC Tool), http://www.sae.org/standardsdev/cdctool/. This tool has been adopted in “AS6171: Test Methods Standard; General Requirements, Suspect/Counterfeit, Electrical, Electronic, and Electromechanical Parts” for the basis of test method selection and evaluation of test effectiveness.

He serves on organizing committees of HOST, VTS, ITC-India, and PAINE. He is on the technical program committees in several reputed conferences, such as DAC, HOST, ITC, VTS, PAINE, VLSID, GLSVLSI, ISVLSI, and Blockchain. He serves in the SAE International G-19A Test Laboratory Standards Development Committee and G-32 Cyber-Physical Systems Security Committee. He is a member of both the IEEE and ACM.

Abstract:
The continuous growth of counterfeit integrated circuits (ICs) in the electronics supply chain calls for an immediate solution as their inferior quality poses serious threats to our critical infrastructures. Information Handling Services Inc. reported that counterfeit ICs represent a potential annual risk of $169 billion to the global electronics supply chain, and the trend continues. Among all counterfeit categories, recycled ICs account for almost 80% of all reported counterfeit incidents. Deploying these recycled chips in critical infrastructure would be catastrophic as they exhibit lower performance and shorter lifespan than a newly manufactured IC. In addition, the crude recycling process of removing ICs from printed circuit boards (PCBs) under extremely high temperatures, followed by sanding, repackaging, and remarking, could potentially create additional defects and anomalies. Moreover, the recycling process may also create latent defects. Although a counterfeit IC may pass the initial acceptance testing by original equipment manufacturers (OEM), it is susceptible to failure in the field.

In this presentation, we first present a robust and low-cost solution for enabling the traceability of an IC. The proposed solution builds a chain of trust among the manufacturer, distributors, and system integrator by providing endto-end traceability in the semiconductor supply chain and protecting against IC recycling. The proposed solution utilizes a small passive radio-frequency identification (RFID) tag, which needs to be placed on the package. Any supply chain entity can verify a chip’s authenticity using a commercial RFID reader.

Second, we present a novel approach to estimating the operational age of ICs by measuring IDDQ, the quiescent current from the power supply, or the total leakage current in steady-state. This current decreases as the circuit ages, largely due to the increase in the magnitude of the PMOS transistor threshold voltage caused by negative bias temperature instability (NBTI). The impact of NBTI on PMOS transistors depends upon the operational stress, that is, the duration of its ON state. Our technique uses the normalized difference, ∆I, computed from current measurements at two input test patterns, as the self-referencing circuit age indicator. The first pattern is chosen such that its IDDQ is controlled by a large number of minimally stressed PMOS transistors. As for the second pattern, the IDDQ is controlled by an approximately equal number of highly stressed PMOS transistors. The difference between these two IDDQ values increases as the circuit ages. This approach requires no hardware modification in the circuit and can be applied even to legacy ICs.

Finally, we show a new and highly effective approach for detecting recycled ICs by exploiting the power-up state of on-chip SRAMs. Our methodology does not require the introduction of any special aging detection circuitry nor a record of historical circuit performance data as its reference. Instead, we exploit the power-up state of an SRAM with an equal number of cells power up to the 0 and 1 logic states to detect prior usage. Since SRAMs exist in virtually all system-on-chips (SoCs), this simple aging detection method can be applied to chips already circulated in the market.

Speaker:

Naghmeh Karimi, UMBC, USA

Title: “Does Device Aging Affect Security?

Bio: 
Naghmeh Karimi received a Ph.D. degree in Computer Engineering from the University of Tehran in 2010. She was a visiting researcher at Yale University, USA between 2007 and 2009, and a post-doctoral researcher at Duke University, USA during 2011-2012. She has been a visiting assistant professor at New York University and Rutgers University between 2012 and 2016. She joined the University of Maryland Baltimore County as an assistant professor in 2017 where she leads the SECure, REliable and Trusted Systems (SECRETS) research lab. She has published three book chapters and authored/co-authored more than 70 papers in refereed conference proceedings and journal manuscripts. She is a senior member of IEEEm and serves as an Associate Editor of the Springer Journal of Electronic Testing: Theory and Applications (JETTA) and IEEE Design \& Test Journal. She has been the corresponding guest editor of the Journal on Emerging and Selected Topics in Circuits and Systems (JETCAS); special issue in Hardware Security in Emerging Technologies in 2021. Her current research interests include hardware security, VLSI testing, design-for-trust, design-for-testability, and design-for-reliability. She is a recipient of the National Science Foundation CAREER Award in 2020.

Abstract:
With the aggressive scaling of VLSI technology, aging-related degradation of integrated circuits has received a lot of attention. Aging changes the specifications of transistors during the time and in turn, the timing and power consumption of the underlying devices. Thereby, agingrelated degradations can affect the success of the physical attacks targeting cryptographic cores through power side-channel attacks or fault injection attacks in order to leak sensitive data. In this presentation, we discuss the aging-induced security concerns in cryptographic devices and show how the security is diminished for some of these physical attacks when the device is aged. We also discuss the countermeasures we developed to provide long-lasting security against such attacks.

Speaker:

Susmita Sur-Kolay, ISI, India

Title: “Challenges in Design of Secure IoT based Industrial and Healthcare Systems

Bio:
Susmita Sur-Kolay has been a faculty at the Indian Statistical Institute and is presently a Senior Professor. She was the Professor-in-Charge of the Computer and Communication Sciences Division of ISI till 2018. She received the B.Tech. degree in electronics and electrical communications engineering from IIT Kharagpur, and the Ph.D. degree in computer science and engineering from Jadavpur University. She was in the Laboratory for Computer Science at Massachusetts Institute of Technology for as a Graduate Research Assistant, a Postdoctoral Fellow at the University of Nebraska–Lincoln, a Reader at Jadavpur University during 1993-1999. She was a Visiting Faculty Member at Intel Corporation, USA in 2002,and a Visiting Researcher at Princeton University in 2012. Her research contributions are in the areas of algorithms for design automation of secure electronic systems and reliable quantum computers, graph algorithms. She has co-authored edited books, several technical papers in leading international journals and refereed conference proceedings, a chapter in the Handbook on Algorithms for VLSI Physical Design Automation. She has served on the committees of many international conferences and Editorial boards of leading journals. She was a Distinguished Visitor (India) of the IEEE Computer Society, an Associate Editor of the IEEE Transactions on Very Large Scale Integration (VLSI) Systems and ACM Transactions on Embedded Computing Systems. She is a Fellow of Indian National Academy of Engineering, among other awards a recipient of the President of India Gold Medal and a Distinguished Alumnus Award of IIT Kharagpur, Women in Technology Leadership Award of the VLSI Society of India.

Abstract:
Internet of Things (IoT), also referred to as the Internet of Objects, is transforming the approach for providing numerous services. Compact and portable lightweight smart devices are an essential part of IoT. They range widely in use, size, energy capacity, and computation power. However, the integration of these smart things into the standard Internet introduces several security challenges because the majority of Internet technologies and communication protocols were not initially designed to support IoT. Moreover, commercialization of IoT has led to public security concerns, including personal privacy issues, threat of cyber attacks, and organized crime. In order to provide a guideline for those who want to investigate IoT security and contribute to its improvement, a comprehensive list of vulnerabilities is provided first along with suitable countermeasures against them.

Most IoT initiatives in healthcare revolved around the improvement of care as such with remote monitoring and telemonitoring as main applications. Wearable medical sensors (WMSs) are garnering ever-increasing attention from both the scientific community and the industry. Driven by technological advances in sensing, wireless communication, and machine learning, WMS-based systems have begun transforming our daily lives.

A second area where many initiatives exist is tracking, monitoring and maintenance of assets on the level of medical devices and healthcare assets, the people level and the non¬medical asset level (e.g. hospital building assets). These deployments are just the beginning and, at the same time, are far from omnipresent. More advanced and integrated approaches within the scope of the digital transformation of healthcare are starting to be used with regards to health data aspects where IoT plays an increasing role, as it does in specific applications such as smart pills, smart home care, personal healthcare, robotics and Real¬Time Health Systems (RTHS).

Notwithstanding all these benefits, Information security has become an important concern in healthcare systems, owing to the increasing prevalence of medical devices and the growing use of wearable and mobile computing platforms for health and lifestyle monitoring. Early works in the area of health information security has largely focused on attacks on the wireless communication channel of medical devices, or on health data stored in online databases. Recent works have also addressed entirely different angles to health information security being motivated by the insight that the human body itself is a rich source (acoustic, visual, and electromagnetic) of data.

Although WMSs were initially developed to enable low-cost solutions for continuous health monitoring, the applications of WMS-based systems now range far beyond health care. Several research efforts have proposed the use of such systems in diverse application domains, e.g., education, human-computer interaction, and security. Even though the number of such research studies has grown drastically in the last few years, the potential challenges associated with their design, development, and implementation are neither well-studied nor well-recognized.

This lecture presents first the different aspects of IoT security and then a couple of scenarios depicting the potential risks. Next, the desiderata for secure healthcare IoT system design are discussed in general, followed by possible cases of inadvertent information leakage. Finally, energy efficiency of health monitoring is addressed and how applications of healthcare IoT systems beyond health monitoring can be built is described.

Invited Talk 2:

Speaker:

Shridhar G Bendi, Sr. Principal Engineer (Intel)

Title: “3D stacked die (Foveros) technology: Concept, HVM test strategy and associated DFT.

Bio:
Susmita Sur-Kolay has been a faculty at the Indian Statistical Institute and is presently a Senior Professor. She was the Professor-in-Charge of the Computer and Communication Sciences Division of ISI till 2018. She received the B.Tech. degree in electronics and electrical communications engineering from IIT Kharagpur, and the Ph.D. degree in computer science and engineering from Jadavpur University. She was in the Laboratory for Computer Science at Massachusetts Institute of Technology for as a Graduate Research Assistant, a Postdoctoral Fellow at the University of Nebraska–Lincoln, a Reader at Jadavpur University during 1993-1999. She was a Visiting Faculty Member at Intel Corporation, USA in 2002,and a Visiting Researcher at Princeton University in 2012. Her research contributions are in the areas of algorithms for design automation of secure electronic systems and reliable quantum computers, graph algorithms. She has co-authored edited books, several technical papers in leading international journals and refereed conference proceedings, a chapter in the Handbook on Algorithms for VLSI Physical Design Automation. She has served on the committees of many international conferences and Editorial boards of leading journals. She was a Distinguished Visitor (India) of the IEEE Computer Society, an Associate Editor of the IEEE Transactions on Very Large Scale Integration (VLSI) Systems and ACM Transactions on Embedded Computing Systems. She is a Fellow of Indian National Academy of Engineering, among other awards a recipient of the President of India Gold Medal and a Distinguished Alumnus Award of IIT Kharagpur, Women in Technology Leadership Award of the VLSI Society of India.

Abstract:
A quick overview of Intel’s 3D stacked die (Foveros) technology and its play in heterogenous chip design world. While this technology provides upside on product goodness front, it poses unique challenges in high volume productization front. As part of this talk, will try providing sneak-peak into High Volume Manufacturing (HVM) challenges, strategy and associated DFT. Towards the end will touch upon potential areas of opportunity for EDA vendors.

Invited Talk 3:

Speaker:

Punit Kishore, Senior Director (NXP)

Title: “Real Cost of Quality Based DFT

Bio:
Punit is Senior Director DFT at NXP®, acts as Global DFT lead for architecture and methodology. Formerly he was Principle at Qualcomm®, where he focused on Automotive DFT strategies and Test-AUC optimizations. He also worked as Design Manager at Qualcomm®, where he managed complete SOC execution. After graduating from IIT Kanpur in Electrical Engineering, he worked at Texas-InstrumentsTM, NVIDIA® and Intel ® prior to Qualcomm®, looking into the DFT of various classes of products. He invented USB based test-strategy for high volume SLT deployment. He holds 7 patents in the field of High-speed-IO DFT, LBIST, HSIO based DFT, Concurrent SCAN.

Abstract:
A framework for assessing the cost of semiconductor device manufacturing and the role of DFT engineering in achieving quality tradeoffs. NXP plays in a very diverse eco-system, where there is varied quality requirement, a case study will be presented to substantiate the framework. This talk will cover architectural elements, device physics, program efficiency, and production management to the dollar.

Event Location

Radisson Blu Hotel, Bengaluru Outer Ring Road

Address: 90/4 Outer Ring Road, Marathahalli, Bengaluru, 560037, India

Google Maps Direction: https://goo.gl/maps/nyvHRWcNstifH6TE6