Title: “Meeting Testing challenges – An Integrated Approach“
Jian is a semiconductor industry veteran with more than 25 years of experience in process technology development, foundry operations, product engineering. Jian has extensive experience in leading and integrating global teams from various regions and businesses, having spent more than a decade in the U.S. and Asia.
Jian is the Vice President in Qualcomm, leading the Product Test Engineering (PTE) in APAC, responsible for new product test development, characterization, and test deployment, yield management, integrating and optimizing performance for all products across the BUs. She also oversees technical and management coordination with the PTE teams in the U.S.
Prior to Qualcomm, Jian served as VP of technology at NXP, responsible for technology roadmap planning and execution, both for in-house fabs and foundries. She also partnered with foundry and internal teams to ensure all new products and foundry processes would meet the automotive quality requirements and work.
Jian held various management positions, including Global Foundries and Hewlett Packard. She holds master’s and bachelor’s degree in Electrical Engineering from Purdue University.
IC industry is in another “Golden Age”, widely recognized for both strategic and commercial values. The powerful drive towards intelligent connected world, real and virtual, puts unprecedented demands on faster, better, affordable products. Transition to heterogeneous integration and leading edge technologies pose further challenges in product testing – in areas of DFT, Diagnosis, In-Test Thermal/Power Management to name a few. Automotive quality requires new thinking in test for margin. An integrated approach, starting with meticulous DFT & EDA solutions architected upfront, coupled with quick learning from Terabytes of Testing Data, is needed to solve tomorrow’s problem. We, at Qualcomm continue to be excited about the future of DFT & Test opportunities in the days ahead.
Title: “DFT to In-Life monitoring for dependable electronic systems“
Ankur Gupta is Vice President and General Manager of Tessent Test and Embedded Analytics business at Siemens EDA. Formerly he was head of Product Management and Applications at Ansys, Semiconductor and Head of Applications Engineering for Digital Implementation & Signoff at Cadence Design Systems.
Ankur has 20+ years of experience in EDA, working on some of the industry’s most innovative Digital Design, Implementation and Signoff products. He holds 4 US Patents and a Master’s Degree in Electrical and Computer Engineering, from Iowa State University.
The reliable and secure operation of electronics, i.e., healthy electronics, in safety-critical, enterprise servers and cloud computing domains is a major challenge. Traditionally, manufacturing test solutions were intended to guarantee the in-life reliability and security of electronic systems. However, as the diversity and complexity of software workloads drive huge increases in the complexity of these systems, unexpected inefficiencies, anomalies, and vulnerabilities cause outsized effects on the end application. This is a drag on business performance. Therefore, the solutions for in-life management need to extend beyond robust design-for-test. Sensors and monitors must be embedded in different levels of the design stack, providing both structural and functional views of the system, with a solution that is built on a foundation of strong industry leading products and industry standard access mechanisms as well as data analytics that run on the edge and in the cloud. To drive successful business outcomes, the industry must consider investing in key technology components, including trusted design-for-test platform, silicon-proven functional monitors and analytics that deliver actionable outcomes.
Title: “Silicon Lifecycle Management: Trends, Challenges and Solutions“
Dr. Yervant Zorian is a Chief Architect and Fellow at Synopsys, as well as President of Synopsys Armenia. Formerly, he was Vice President and Chief Scientist of Virage Logic, Chief Technologist at LogicVision, and a Distinguished Member of Technical Staff AT&T Bell Laboratories. He is currently the President of IEEE Test Technology Technical Council (TTTC), the founder and chair of the IEEE 1500 Standardization Working Group, the Editor-in-Chief Emeritus of the IEEE Design and Test of Computers and an Adjunct Professor at University of British Columbia. He served on the Board of Governors of Computer Society and CEDA, was the Vice President of IEEE Computer Society, and the General Chair of the 50th Design Automation Conference (DAC) and several other symposia and workshops.
Dr. Zorian holds 35 US patents, has authored four books, published over 350 refereed papers and received numerous best paper awards. A Fellow of the IEEE since 1999, Dr. Zorian was the 2005 recipient of the prestigious Industrial Pioneer Award for his contribution to BIST, and the 2006 recipient of the IEEE Hans Karlsson Award for diplomacy. He received the IEEE Distinguished Services Award for leading the TTTC, the IEEE Meritorious Award for outstanding contributions to EDA, and in 2014, the Republic of Armenia’s National Medal of Science.
He received an MS degree in Computer Engineering from University of Southern California, a PhD in Electrical Engineering from McGill University, and an MBA from Wharton School of Business, University of Pennsylvania.
Recent growth in utilizing AI Accelerators, in data centers and automotive SOCs have led to an explosion in the adoption of emerging technology nodes and 3DIC/chiplet packages. This keynote will first present today’s trends, then concentrate on resiliency challenges for such emerging SOCs, and then will discuss optimizing their health using advanced solutions, which are typically utilized for managing all the silicon lifecycle stages: from silicon debug in early bring up stage to shorten the time-to-market; to self-test and repair during volume production stage to improve quality and yield; to power-on self-test in the field to address aging defects; to in-system periodic checking in the field to improve functional safety; and finally to fault tolerance and error correction during the mission mode to address a range of transient errors. All of the above are realized by on-chip and off-chip data analytics.
Title: “Convergence of SLT & ATE for SoC manufacturing test screening“
Sajjad Pagarkar is Head of Post Silicon Engineering in the Core Technology Division at Google. He has led Product development and test engineering teams of numerous complex SoC’s in the past 22 years, enabling shipping of billions of mobile & compute chips. For the last 10 years Sajjad has extensively worked on development of SLT from ground zero to massively parallel screening solutions to enable high volume productization of SOC’s from 16nm down to 4nm technologies. When Sajjad is not at his desk, you can find him hiking in the woods of his home state, California.
The outgoing quality requirement & time to high volume production of today’s mobile/compute/AI SoC are significantly tighter than those for the conventional SOC’s. Bringing products with shorter time to market with low DPPM in latest semiconductor process technology nodes have created many challenges in DFT & post silicon high volume production screening domains. We need a very sound test strategy to manage low outgoing DPPM with optimum cost of test. The unique challenges associated with productization of mobile/compute/AI SOCs will be addressed in the talk, along with our experience in overcoming them.
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