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Agenda
Tutorials:
| Sunday | 24 July, 2022 | |||
|---|---|---|---|
| 8:00 am - 9:30 am | REGISTRATIONS | ||
| TRACKS |
TRACK 1 Session Chair | Dr. Subhadip Kundu |
TRACK 2 Session Chair | Shamitha Rao |
TRACK 3 Session Chair | Prof. Sivanantham |
| HALL NAME | GRAND VICTORIA - A | GRAND VICTORIA - B | ARABICA & ROBUSTA |
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9:30 am - 11:00 am ( 15 mins Break ) 11:15 am - 12:45 pm |
T1: Scan Test Escapes, New Fault Models, and Effectiveness of Functional System Level Tests
Prof. Adit Singh (Auburn University) |
T2: Basics of Design for Test – Enabling Manufacturing Test
Sreekanth Pai and Balaji Upputuri (Marvell) |
T3: Hierarchical DFT techniques for AI and Large SoCs
Lee Harrison (Siemens) |
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T4: Bridging the Gap Between Design-For-Test and Failure Analysis for Yield and Reliability Improvements
Rakesh Kinger and Gaurav Mattey (Google) |
T5: Challenges and Advances in Power-Aware Testing
Dr. Ankush Srivastava (Qualcomm) |
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| 12:45 pm - 1:45 pm | LUNCH BREAK | ||
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1:45 pm - 3:15 pm ( 15 mins Break ) 3:30 pm - 5:00 pm |
T6: A Complete DFT Methodology from Chip Planning to Implementation
Niranjani Sukumar and Salvatore Talluto (Synopsys) |
T7: Addressing Test, Safety and Security for Connected Automotive IC’s
Lee Harrison and Dr. Nilanjan Mukherjee (Siemens) |
T8: Challenges of High Accuracy and Low-cost Test for Analog Power ICs, and the future Trends
Gaurav Mittal (Texas Instruments) |
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T9: Practical aspects of Implementing IEEE 1687
Rajesh Khurana and Dr. Vivek Chickermane (Cadence), Balaji Upputuri (Marvell) |
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Conference | Day 1
| Monday | 25 July, 2022 | ||
| 8:00 am - 9:15 am | REGISTRATIONS | |
| 9:00 am - 9:25 am | Inauguration/Welcome | Sameer Chillarige, General Co-Chair, ITC India 2022 | |
| 9:25 am - 9:30 am | Special Guest Talk | |
| 9:30 am - 10:15 am | Keynote 1: Meeting Testing challenges – An Integrated Approach, Jian Zhang, Qualcomm | |
| 10:15 am - 11:00 am | Keynote 2: DFT to In-Life monitoring for dependable electronic systems, Ankur Gupta, Siemens EDA | |
| 11:00 am - 11:30 am | TEA/COFFEE BREAK SESSION | |
| SESSIONS |
Session 1 - Advancements in Design For Test Session Chair | Dr. Ankush Srivastava |
Session 2 - 3DIC test challenges & Advanced Fault Models Session Chair | Srinivasan Chandra Sekaran |
| HALL NAME | GRAND VICTORIA - A | GRAND VICTORIA - B |
| 11:30 am - 1:00 pm |
1.1 Enhancing At-Speed Testability of Complex Inter-Core IO Interfaces, Wilson Pradeep, Muniswara Vorugu and Vevekanenda Gonugunta 1.2 Selective Multiple Capture Test (SMART) XLBIST, Peter Wohl, John Waicukauski, Anushree Bhat, Vijay Kumar K S and Rajit Karmakar 1.3 A novel fully automated multi-mode scan stitching architecture, Sarthak Singhal, Puneet Arora, Subhasish Mukherjee, Raghav Khemka and Krishna Chakravadhanula |
2.1 TSV BIST Repair : Design-for-Test Challenges and Emerging Solution for 3D Stacked IC’s, Akkapolu Sankararao, Vaishnavi G and Malige Sandya Rani 2.2 Accurate Diagnosis of Cell Internal Defects with Multiple Excitation and Propagation Conditions, Sonam Kathpalia, Sameer Chillarige, Bharath Nandakumar, Madhur and Santosh Malagi 2.3 An Efficient Test Time Model for Optimizing Tessent SSN for a 3D Design, Vasubabu Ravipati, Shyam N Kallepalli and Lance C Cheney |
| 1:00 pm - 2:00 pm | LUNCH BREAK | |
| SESSIONS |
Special Session - Security Session Chair | Subhasish Mukherjee |
ART Track Session Chairs | Dr. Ankush Srivastava & Prof. Usha Mehta |
| HALL NAME | GRAND VICTORIA - A | GRAND VICTORIA - B |
| 2:00 pm - 3:30 pm |
Recent Advancement in Detecting Recycled ICs, Prof. Ujjwal Guin, Auburn University Does Device Aging Affect Security?, Prof. Naghmeh Karimi, UMBC, USA Challenges in Design of Secure IoT based Industrial and Healthcare Systems, Prof. Susmita Sur-Kolay, ISI, India |
Analog, RF and mixed-signal IC Testing using AI enhanced alternate tests, Anshaj Shrivastava, IISc Bangalore Reliable and Fault-Tolerant Physically Unclonable Functions, Syed Farah Naz, IIT Jammu ML-Assisted Testing of Digital Circuits, Shruti Pandey, IIT Delhi Securing the test infrastructure of SoCs, Anjum Riaz, IIT Jammu Design of Efficient Programmable and Reconfigurable Pseudorandom Test Pattern Generator, Geethu R S, Amrita School of Engineering |
| 3:30 pm - 4:00 pm | TEA/COFFEE BREAK SESSION | |
| SESSIONS |
Panel Discussion - 1 Session Chair | Kamlesh Pandey |
Poster Session Session Chair | Santosh Kumar & Bharath Nandakumar |
| HALL NAME | GRAND VICTORIA - A | GRAND VICTORIA - B |
| 4:00 pm - 5:30 pm |
The Conundrum of Low Power Testing: Challenges, Solutions, and Associated Cost
Panelists: 1. Dr. Rubin Parekhji (TI) 2. Prof. Adit Singh (Auburn) 3. Dr. Nilanjan Mukherjee (Siemens) 4. Gaurav Bhargava (Qualcomm) 5. Parthajit Bhattacharya (Synopsys) |
Posters |
| 5:30 pm - 6:30 pm | High Tea | |
Conference | Day 2
| Tuesday | 26 July, 2022 | ||
| 8:00 am - 9:15 am | REGISTRATIONS | |
| 9:15 am - 9:30 am | Welcome / Day 2 Summary | Kamlesh Pandey, General Co-Chair, ITC India 2022 | |
| 9:30 am - 10:15 am | Keynote 3: Silicon Lifecycle Management: Trends, Challenges and Solutions, Yervant Zorian, Synopsys | |
| 10:15 am - 11:00 am | Keynote 4: Convergence of SLT & ATE for SoC manufacturing test screening, Sajjad Pagarkar, Google | |
| 11:00 am - 11:30 am | TEA/COFFEE BREAK SESSION | |
| SESSIONS |
Session 3 - Optimizations in Silicon Manufacturing & Test Application Session Chair | Srinivas Vooka |
Session 4 - Test Methodology, Validation and Power Aware Test Session Chair | Bharath Nandakumar |
| HALL NAME | GRAND VICTORIA - A | GRAND VICTORIA - B |
| 11:30 am - 1:00 pm |
3.1 Transfer-Matrix Abstractions to Analyze the Effect of Manufacturing Variations in Silicon Photonic Circuits, Pratishtha Agnihotri, Priyank Kalla and Steve Blair 3.2 Towards Complete State Machine Traversal via Pseudo Transitions in Automated Lab Verification, Marc Huppmann, Manuel Harrant, Thomas Nirmaier, Andi Buzo, Linus Maurer and Georg Pelz 3.3 Implementation of Monotonicity Testing Utilizing On Chip Resources for Test Time Reduction, V Hemanthkumar |
4.1 Test Methodology Automation for Multi-Die Package Realization, Durga Prasad Bade, Rohini Gulve, Adam Cron and Mike Ricchetti 4.2 Design of a programmable low power linear feedback shift register for BIST application, Maragathaeswari B and Geethu Remadevi 4.3 A System-Level Post-Silicon Validation Methodology for High-Speed Serial Interfaces, Sudeep Puligundla, Manikandan T, Paul Sunderland, Vineeth Vl, Anshu Gupta, Felix Tudoran, Christopher Daffron, Moises Puga Nathal, Tim Linn, Wayne Huang, Saikiran V, Sukay Luhadia and Scott Gardiner |
| 1:00 pm - 2:00 pm | LUNCH BREAK | |
| SESSIONS |
TRC Track Session Chair | Anurag Jain & Vishal Vadhavania |
Session 5 - Design for Security & Analog Test Session Chair | Prof. Jayagowri |
| HALL NAME | GRAND VICTORIA - A | GRAND VICTORIA - B |
| 2:00 pm - 3:30 pm |
TRC 1 Enabling Hierarchical Assembly Build (MSIE) to improve turnaround time and performance for DFT pattern verification, Anuj Gupta, Sudhakar Kongala and Om Prakash Mishra TRC 2 Enhanced Diagnosis on Scan and Memory Failures for 22ULL Tech Node, Arul Karthick Kumar, Vivek Roopchand and Balaji Duthae Srinivasan TRC 3 Validation Strategies to Achieve Zero Silicon bugs in DFT Logic, V N Sivakumar Avvaru, Souvik Sarkar, Prakash Kumar and Ashutosh Anand TRC 4 A Novel approach of improving test coverage using Z01X functional fault grading technique, Sreenivasa Rao Vuttaravilli, Leela Krishna Thota and Srinu Kona |
5.1 A Threshold based Hardware Trojan Detection Technique Using XGBoost Algorithm, Ranit Das, Tapobrata Dhar and Surajit Kumar Roy 5.2 Performance Enhancement of Unsupervised Hardware Trojan Detection Algorithm using Clustering-based Local Outlier Factor Technique for Design Security, S Meenakshi and Nirmala Devi M 5.3 Functional Testing of On-chip Analog/RF Circuits using Machine Learning based Regression Models, Anshaj Shrivastava and Gaurab Banerjee |
| 3:30 pm - 4:00 pm | TEA/COFFEE BREAK SESSION | |
| SESSIONS |
Invited Talks Session Chair | Kavitha Shankar |
Panel Discussion - 2 Session Chair | Dr. C P Ravikumar |
| HALL NAME | GRAND VICTORIA - A | GRAND VICTORIA - B |
| 4:00 pm - 5:30 pm |
1. Real Cost of Quality Based DFT, Punit Kishore, NXP 2. 3D stacked die (Foveros) technology: Concept, HVM test strategy and associated DFT, Shridhar Bendi, Intel |
Talent Development in Test/Validation Domains Panelists: 1. Binoy Maliakal (TI) 2. Pathy Iyer (Keysight) 3. Rajesh Vaddempudi (Tessolve) 4. Prashant Narang (Cadence) 5. Venkat Sunkara (ChipEdge) |
| 5:30 pm - 5:45 pm | Closing Ceremony | |
Event Location
Radisson Blu Hotel, Bengaluru Outer Ring Road
Address: 90/4 Outer Ring Road, Marathahalli, Bengaluru, 560037, India
Google Maps Direction: https://goo.gl/maps/nyvHRWcNstifH6TE6