Back in 2019, I had started my career as an R&D engineer working for Cadence, within the Modus ATPG  and DFT product group. I got an opportunity to participate in my first International Test Conference (ITC) – ITC India 2019. Since its inception in 2017, ITC India is being held annually in Bengaluru, and has seen increasing interest and participation over the years. It serves as a platform for the Test-DFT-EDA engineering and the academic fraternity to contribute towards solving the grand challenges in VLSI Test. 

In 2019, ITC India was conferred the title of “Most Successful Technical Meeting Award” by the Test Technology Council (TTTC). Indeed, a commendable achievement and a matter of great pride for the ITC India organizing committee.

ITC India 2019 was held from 21st July to 23rd July 2019, at the Leela, Bengaluru. It kicked-off with Day 1 dedicated to 6 parallel tutorial tracks. I chose – “AI Chip Technologies and DFT Methodologies” and “Creation and Selection of Fault Models for Defect Based Testing”. Both the tutorial sessions were well presented, and I enjoyed being a part of these sessions. 

Day 2 started off with a welcome address by the ITC India General Chair – Navin Bishnoi, followed by the ceremonial inauguration. Dr. Yervant Zorian, Chairman TTTC, was the next speaker who talked about “50 years of ITC”, highlighting the role played by the TTTC and its various conferences. Michael Campbell, VP Qualcomm another speaker, talked about 5G and how this would drive the future of connected products and innovation. Mike’s talk was interesting, as it had rich illustrations on the importance of test, and how the small fraction of ‘unmodeled defects’ could be the ‘devil in the detail’. He called upon test engineers, EDA vendors and ATE  manufacturers to respond to the requirements of the 5G era and develop innovative solutions involving AI/ML techniques for the complete design-fab-test loop. The audience also had an opportunity to listen to other renowned names in the VLSI test industry who talked about diverse topics such as test quality and test economics, automotive test, hardware-software co-design, defect-based test etc. We broke for coffee and started with the technical presentations.

Day 3 was mostly about technical presentations. Kaushik Narayanun from Nvidia, talked about DFX and why it was important for the semiconductor business. A talk by Japanese researchers on RTL level scan synthesis was very insightful, and well appreciated by the audience. Post the RTL scan synthesis presentation, I had my talk on how the Defect Detection Matrices (DDMs) generated during cell-aware library characterization be optimized for achieving better ATPG coverage. The last talk I attended was on DFT challenges for server chips by Nagesh Tamarapalli from AMD. This was followed by a closing ceremony, and announcement of several awards. Finally, ITC India 2019 came to a meaningful conclusion after 3 days of stimulating discussions and interesting technical talks.