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Call for Papers
Call For Submissions
Important Dates :
Regular Papers:
✓ Abstract submission deadline : 17 March, 2025
✓ Paper submission deadline : 24 March, 2025
✓ Author notification : 19 May, 2025
✓ Final manuscript due : 9 June, 2025
AUTHOR INSTRUCTIONS: Please check this document (updated) for instructions of Final Paper Submissions.
Please note: Full length paper submission along with the abstract is allowed till submission deadline date.
Please note: We require the authors to follow this paper template: CFP template (CAMERA READY)
Posters:
✓ Poster submission deadline : 19 May, 2025
✓ Author notification : 9 June, 2025
The Call For Papers for ITC Test Week India is live!
International Test Conference is the world’s premier venue dedicated to the electronic test of devices, boards and systems—covering the complete cycle from design verification, design-for-test, design-for-manufacturing, silicon debug, manufacturing test, system test, diagnosis and failure analysis, and back to process and design improvement. At ITC India, design, test, and yield professionals can confront challenges faced by the industry, and learn how these challenges are being addressed by the combined efforts of academia, design tool and equipment suppliers, designers, and test engineers. This ITC India conference will be blend of virtual & direct participation focusing on Test development in India but the submissions may not be limited to topics related to this region. Topics related to design and test development across any geographical regions will be of interest.
Authors are invited to submit original, unpublished papers describing recent work in the field of test and design. In addition, authors are invited to submit high quality, practical, industry best practices. Submissions simultaneously under review or accepted by another conference, symposium or journal, will be summarily rejected. Accepted papers will be submitted for inclusion into IEEE Xplore subject to meeting IEEE Xplore’s scope and quality requirements.
Authors are also invited to submit a single-page poster proposal, double-columned in Format (template available in EasyChair). Posters are a useful way of presenting late-breaking results, getting feedback on an innovative method, or participating without having to write a full paper.
Note: For detailed information about the submission process, requirements and deadlines, the selection process and any other questions regarding the program itself or contact information, please consult the ITC India web site at https://www.itctestweekindia.org or email the program chair at itc-india-[email protected]
Submission Guidelines
- One or two topic(s) from the topic list, or a description of your topic.
- An abstract of 35 words or less to be entered online
- An electronic copy of a complete paper up to 6 pages, double-columned in IEEE Format, A4 size
(https://www.ieee.org/conferences/publishing/templates.html) to be submitted through EasyChair (https://easychair.org/conferences/?conf=itcindia2025). Submissions less than 4 pages are rarely accepted. - Your submission must not include information that serves to identify the authors of the manuscript, such as name(s) or affiliation(s) of the author(s), anywhere in the manuscript, abstract, or in the embedded PDF data. References and bibliographic citations to the author(s) own published works or affiliations should be made in the third
person
ITC India invites submissions on the latest advances in test, validation and diagnosis of ICs, boards and systems.
Topics of interest include (not limited to)
3D/2.5D Test
RF, mm-Wave and THz testing
Adaptive Test in Practice
ATE/Probe Card Design
Advances in Boundary Scan
Bring Up
Data Driven Methods
Data Exchange and Infrastructure
Defect-Oriented Testing
DFM and Test Diagnosis
Economics of Test
End-to-End Data Analysis
Embedded BIST & DFT
Emerging Defect Mechanisms
Hardware Security and Trust
IoT Testing
Known-Good-Die testing
Memory Test and Repair
MEMS Testing
Mixed-Signal and Analog Test
New Technologies and Test
On-Chip Test Compression
Online Test
Pre- and Post- Silicon Validation
Power Issues in Test
Protocol-aware Test
Reliability and Resilience
Scan Based Test
SoC/SiP/NoC Test
Silicon Debug
Jitter, High-Speed I/O and RF Test
Simulation and Test
System Test (Applications)
System Test (Hardware/Software)
Test-to-Design Feedback
Test Escape Analysis
Test Flow Optimizations
Test Generation and Validation
Test Resource Partitioning
Test Standards
Test Time Analysis and Reduction
Testing High Speed Optics/Photonics
Timing Test
Yield Analysis and Optimization
Conference Location
Radisson Blu Hotel, Bengaluru , India. (Marathahalli, Outer Ring Road)
Address: 90/4 Outer Ring Road, Marathahalli, Bengaluru, 560037, India
Google Maps:
Click here for Direction
To Be Decided (TBD)