Recent growth in content delivery has led to an explosion in the use of embedded memories. This tutorial will present the trends and challenges of growing memory content on chip and how to ensure detection of today’s defects upon manufacturing and during life time, including process variation and FinFET specific defects including 7nm technology. BIST and Repair solutions to address debug, diagnosis, yield optimization and data retention of failure modes will be presented. Given the tens of thousands of embedded memory instances in today’s SOCs, this tutorial will also cover power management constraints, functional timing implications, test scheduling optimization, and area minimization options.
Dr. Yervant Zorian is a Chief Architect and Fellow at Synopsys, as well as President of Synopsys Armenia. Formerly, he was Vice President and Chief Scientist of Virage Logic, Chief Technologist at Logic Vision, and a Distinguished Member of Technical Staff AT&T Bell Laboratories. He is currently the President of IEEE Test Technology Technical Council (TTTC), the founder and chair of the IEEE 1500 Standardization Working Group, the Editor-in-Chief Emeritus of the IEEE Design and Test of Computers and an Adjunct Professor at University of British Columbia. He served on the Board of Governors of Computer Society and CEDA, was the Vice President of IEEE Computer Society, and the General Chair of the 50th Design Automation Conference (DAC) and several other symposia and workshops.
The modern electronic systems we use today are predominantly a combination of Hardware(HW) and Software(SW). Typically, System on a Chip (SoC) IC’s are at the heart of these products, running embedded SW across multiple CPU cores, and communicating with the rest of the product and the user through a multitude of I/O protocols. Developing and validating these SoC’s is a challenging task due to the sheer complexity of the HW, SW, and their overall interaction.System validation of the SoC is required to ensure that the overall product requirements have been met before general release to manufacturing. Use case testing in both pre-silicon and post-silicon validation is becoming a key activity in SoC Validation and being able to leverage tests and functional coverage from pre-silicon to post-silicon is seen as a key contributor to reducing functional escapes to customers and improving time to market. This tutorial will focus on methods and examples of extending the validation continuum from pre-silicon to post-silicon, based on the work from the IEEE CEDA System Validation and Debug Technology Committee’s Coverage Working Group.
Nagabhushan Reddy is currently working as Platform Architect at Intel Technology India Pvt Ltd. He has been working on the Power Management (Modern Standby) Enabling, Debug and Validation Activities on Intel Core Platforms from last several years. He did his B.Tech in ECE from S.K.University and Masters from BITS, Pilani. He started his career as Product Engineer at Havells India Pvt Ltd working on the development of Static Energy Meters and later worked with various companies (across various domains) Bharat Electronics Ltd (RADAR division), Philips Innovation Centre (worked on UPNP, DLNA, Car DVD players), Texas Instruments (Validation-Post Silicion, SysLink etc). Currently, He is a member of IEEE CEDA System Validation and Debug Technology Committee’s Coverage Working Group and working for Validation Coverage Methodology improvements and standardization.
Gaurav Verma is Senior Design Engineer at NXP India Private Limited. He received his B.Tech degree from Indian Institute of Technology Roorkee, India in 2007. Since then, he has been working with NXP Semiconductors where he has developed multiple frameworks for Validation and worked on System & IP Validation. His experience includes Validation Coverage Framework, Electrical Validation and Tooling, JTAG based tools and Validation, Networking Datapath Sub-System Validation, FPGA Based Solutions, Silicon Bring up and web-based Applications. Currently, He is a member of IEEE CEDA System Validation and Debug Technology Committee’s Coverage Working Group and working for Validation Coverage Methodology improvements and standardization.
Ashish Gupta is System Validation Engineering Manager at NXP India Private Limited. He received his B.Tech degree from Indian Institute of Technology Dhanbad, India in 2002 and M. Tech degree from Indian Statistical Institute, Kolkata in 2004. He started his career in Novell Software where he worked on Image compression algorithms for remote VNC management. He also worked in Nvidia Graphics Private Limited as ASIC design engineer and worked on MPEG4 video encoder/decoder SoC (currently known as Tegra series) powering handheld/mobile devices. After that he joined Freescale/NXP in 2007 and mainly worked in areas of system validation and infrastructure development. His experience includes Image, Video processing, Validation Infrastructure and Methodology, System Validation in areas of Core Subsystem wired and wireless Networking. Currently, He is a member of IEEE CEDA System Validation and Debug Technology Committee’s Coverage Working Group and working for Validation Coverage Methodology improvements and standardization.
Hardware acceleration for Artificial Intelligence (AI) is now a very competitive and rapidly evolving market. In this tutorial, we will start by covering the basics of deep learning. We will proceed to give an overview of the new and exciting field of using AI chips to accelerate deep learning computations. It will cover the critical and special characteristics and the architecture of the most popular AI chips. Next we will summarize the features of the AI chips from design-for-test (DFT) perspective and introduce the DFT technologies that can help testing AI chips and speeding up time-to-market. Finally, we will present a few case studies on how DFT is implemented on the real AI chips.
Dr. Yu Huang is a Principal Engineer in the Silicon Test Systems Division of Mentor, A Siemens Business. His research interests include VLSI SoC testing, ATPG, compression and diagnosis. He holds 27 US patents and has 11 patents pending. He has published more than 110 papers in leading IEEE Journals, conferences and workshops. He is a senior member of the IEEE. He has served as technical program committee member for DAC, ITC, ATS, ETS, ASPDAC, NATW and other conferences and workshops in the testing area. He received a Ph.D. from the University of Iowa in 2002.
Rahul Singhal is a Technical Marketing Engineer with Tessent Solutions group of Mentor, A Siemens Business. His focus is on the industry requirements in the areas of ATPG, compression, low pin count testing and DFT for AI chips architectures. He is currently a program committee member of NATW. Rahul received his M.S. in Electrical and Computer Engineering from Portland State University in 2011.
Lee Harrison is a World Wide DFT Service Manager with Mentor, A Siemens Business. He has 20 years of industry experience with Mentor consulting team and has been involved in the specification of new test features and methodologies for Mentor customers delivering high quality DFT solutions. He has extensive experience in AI chips and the specific DFT requirements for AI chips. Lee Received his BEng in Micro Electronic Engineering from Brunel University London in 1996.
Test generation has used the simplifying premise of approximate fault models to model real-life defects in silicon. This approximation has been the basis for the success of ATPG (automatic test pattern generation) tools which are ubiquitously used for today’s designs. This tutorial provides an in-depth understanding of the evolution and choice of fault models as defects become increasingly parametric, (i.e. granular as against gross), for today’s technologies, and how matching ATPG capabilities have been developed to catch these defects, while still keeping the test application time affordably low. While these methods are well developed for digital circuits, they are still evolving for analog circuits. The tutorial will also explain how these methods can be extended to analog circuits and the resulting challenges therefrom. Capabilities built into EDA tools will also be presented.
Rubin Parekhji has been with Texas Instruments, Bangalore, since 1996, where he has led and mentored DFT teams on various design and test technology projects across multiple product groups. More recently, he has been in Kilby Labs and Analog Engineering Operations at TI, working on low cost test methods and test entitlement targets with world-wide teams, as a distinguished member of the technical staff. He has published regularly and delivered tutorials at leading conferences, has mentored a large number of students, and has several issued patents. He has a Ph.D. from Indian Institute of Technology, Bombay, India.
Wilson Pradeep is a Lead DFT Engineer with Texas Instruments, Bangalore. He has over 11 years of experience in DFT and digital front end design. He is currently working as DFT lead for various Industrial and Automotive Radar SoC platform designs at TI. Wilson has authored regular papers in premier test conferences like ITC, ATS and VTS apart from major EDA and TI internal conferences and has several patents covering DFT innovations.
Defining a standard Test Strategy is critical to maximize the efficiency of the product development and reducing test cost. Typically, test industry needs a handful of testers, each of which should be product specific and optimized for cost. Among all these factors Load-Board Design plays a vital role in deciding the overall testability features, Test Quality and cost.
An ATE Load-board is a critical interface part which brings entire capability of ATE instruments to the DUT. An ideal load board should cover full test list with high accurate measurements of the DUT without distorting DUT’s actual performance. An improperly designed load-board may limit the types of tests, diminish the quality of testing, or in worst case, prevent the DUT from being tested at all. Inadequate focus on load board design may have great impact on Silicon bring up, Design Verification, Sample generation, Qualification, etc., in-turn Time to Market. If it happens to Respin the Load board, production release will get impacted to great extent.
The complexity of the Load-Board design will mirror performance requirements of the DUTs like high-speed, Mixed-signal, RF chips which requires a much more complex load-board designs than the low-speed digital chips. In addition to determining measurement needs, choosing the right combination of instruments plays the vital role to test the DUT. If load-board is not designed in a smarter way with the available instrument & right quality, we may end up with multiple test insertions in the production flow which will increase test cost on multiple folds. Such a very drastic ATE load-board design challenges/ best practices are discussed in this Tutorial.
Jagadish Kumar C. is a Director of Test Engineering, Tessolve Semiconductor Pvt. Ltd., Bangalore, India. He has two and half decades of experience in the field of Semiconductor-Test and Product Engineering. He has worked in various leading Companies few of them are Alliance Semiconductor, STATS, Wipro Technologies. He is also a member of IEEE-India. He has led Test Projects across various domains like RF, Analog, Digital, Memory and High speed digital. He is an expert in providing End to End chip testing solution starting from DFT support to Production deployment. He is specialized in developing novel methodology for validating silicon in ATE. He has headed ATE, Product, Test, Characterization, Pattern Generation and Hardware Teams. He has designed various cutting edge Probe cards and ATE load boards. He has worked on various leading ATE giants like Advantest, Teradyne, Credence, LTX, etc.
Srinivasan.C has over eighteen years of experience in the field of Semiconductor-Test and Product Engineering. He is an expert in the area of developing ATE test solution for various multi core SoC. He has leaded the team to test recently launched power management SoCs. He is specialized in various ATEs like 93K, Sapphire, Catalyst, J750, UFlex, etc. He presently works for Tessolve Semiconductor Pvt. Ltd., Bangalore, India as a Senior Manager – Test Engineering.
GowriShankar.I, is a M.Tech graduate from Anna University has worked as a RF Design and Test Engineer. He has published his manuscript on International Journal for Scientific and Engineering Research and presented his paper on International Conference (ICDASDC-2013). He presently works for Tessolve Semiconductor Pvt. Ltd, Bangalore, India as a Test Engineer.
Ever-increasing design complexity and size add weeks to DFT implementation & ATPG time while the schedule continues to shrink. New trends such as SoCs with heavily repeated blocks for AI further underscore the impracticality of testing large complex designs using traditional flat approaches. In this tutorial, we demonstrate how you can successfully and efficiently implement an RTL-based hierarchical methodology that is compatible with all DFT hardware including MBIST and LBIST.
Using a divide-and-conquer approach, test implementation, pattern creation, test application, and diagnosis times are significantly reduced. This reduces risk to schedule as it enables DFT implementation and pattern generation tasks to occur early in the design flow, enable plug-n-play, and localize the impact of late changes (ECOs).
Jay Jahangiri is the ATPG and Compression Product Manager for Tessent products at Mentor, a Siemens Business. He has over 23 years of experience in various DFT disciplines including ATPG, BIST, and boundary scan. Jay worked as a DFT engineer for Texas Instruments and Raytheon prior to joining Mentor. He has been awarded two US patents related to silicon test and holds a Bachelor of Science degree in Electrical Engineering and an MBA. Jay has published numerous papers and articles in the area of silicon test.
Nagesh Tamarapalli has been with AMD India Design Center since 2006. He is currently a Senior Fellow and leads DFT and manufacturing test for AMD server SoCs. Prior to AMD, he was with Mentor Graphics DFT group for about a decade where he worked on logic BIST, test kompression and diagnosis tools. A paper he co-authored at International Test Conference 1999 on logic BIST was awarded Honorable Mention Award. He is also a co-inventor of 18 approved US patents in the area of testing. He has delivered DFT seminars in India and USA at several conferences including VLSI Design conference 2006, 2008, 2012 and 2013, ISQED 2007 and DAC 2008. He holds MS in Electrical Engineering from Indian Institute of Technology, Kharagpur, India and PhD in Electrical Engineering from McGill University, Montreal, Canada.