Test Reality Check Track

Call for Submissions

International Test Conference the world’s premier venue dedicated to the electronic test of device, boards and system, will for the first time host a dedicated Test Reality Check (TRC) track.

Important Dates

  • Presentation Submission deadline : 16 May, 2021
  • Author Notification : 13 June, 2021
  • Final Manuscript Due : 10 July, 2021

The objective of this track is to provide an informal platform for Chip Designers, EDA solution providers as well as academia to present their success stories, state specific burning test issues of their respective product lines and debate about any specific test topic of interest to test community at large The TRC track comprises of the following three sections

  • User Stories The designers can present their test success stories, best practices that lead to reduced turnaround time, test quality improvements or eliminating human errors
  • Data Blitz This is all about unsolved test issues that have no or very limited solutions at present or is a work in progress This section provides opportunity to any individual to describe the issue briefly and seek opinions as well as solutions from test community
  • Panel Discussions A panel of notable industry test experts and academicians will discuss/debate about chosen test topic with active participation from the audience

Submission Guidelines Selection Criteria

The TRC track does not require formal full paper for an entry

Authors are invited to submit a crisp power point presentation regarding their talk for this track The presentations from this track will not be published in IEEE Explore as part of ITC main conference proceedings

  • For User Stories section, a full presentation with title needs to be submitted as an entry The duration of the presentation shall not exceed 25 minutes and 5 minutes will be reserved for Q A The entries will be selected based on the practicality, novelty, versatility and tangible benefits based on real time data from industrial designs
  • For Data Blitz section, a clear description of a problem in a couple of power point slides deck can be submitted as an entry The entries will be selected based on the criticality and clarity of the problems Each speaker will be given 15 minutes for their problem description and another 5 minutes for the audience feedback and discussion
  • For Panel Discussion, interesting and debatable test/DFT topics can be submitted as an entry The best entry will be chosen for a panel discussion The duration of the discussion will be 30 minutes

TRC Track Co-Chairs : TBD

Topics of interest include (not limited to)

3D/2.5D Test

RF, mm-Wave and THz testing

Adaptive Test in Practice

ATE/Probe Card Design

Advances in Boundary Scan

Bring Up

Data Driven Methods

Data Exchange and Infrastructure

Defect-Oriented Testing

DFM and Test Diagnosis

Economics of Test

End-to-End Data Analysis

Embedded BIST & DFT

Emerging Defect Mechanisms

Hardware Security and Trust

IoT Testing

Known-Good-Die testing

Memory Test and Repair

MEMS Testing

Mixed-Signal and Analog Test

New Technologies and Test

On-Chip Test Compression

Online Test

Pre- and Post- Silicon Validation

Power Issues in Test

Protocol-aware Test

Reliability and Resilience

Scan Based Test

SoC/SiP/NoC Test

Silicon Debug

Jitter, High-Speed I/O and RF Test

Simulation and Test

System Test (Applications)

System Test (Hardware/Software)

Test-to-Design Feedback

Test Escape Analysis

Test Flow Optimizations

Test Generation and Validation

Test Resource Partitioning

Test Standards

Test Time Analysis and Reduction

Testing High Speed Optics/Photonics
Timing Test

Yield Analysis and Optimization