Jyotika Athavale is a Senior Technical Leader in Functional Safety at NVIDIA. Prior to this role, she worked as Principal Engineer and lead Functional Safety Architect at Intel Corporation. She is a recognized industry expert with in-depth technical knowledge of platform technologies and architectures for Automotive, Transportation and Avionics Safety Critical Systems, with specific expertise in radiation effects modeling for soft-errors performance. Based in the US, her 24 years of industry career experience in the semiconductor and EDA industry has spanned technical leadership positions as well as management roles.
Jyotika is currently leading and influencing international standards activities in the area of functional safety and dependability. She chairs the IEEE P2851 WG standard on functional safety interoperability and is a board member of the IEEE Computer Society Board of Governors. She is also a Distinguished Visitor with the IEEE Computer Society and is an IEEE Senior Member. Jyotika has authored several IEEE publications and is a core team member of the IEEE Computer Society Special Technical Community for Reliable, Safe, Secure and Time Deterministic Intelligent Systems. She holds a master’s degree in electrical engineering from Iowa State University.
Hardware ASIC / System Safety are key enablers for the overall robustness and dependability of autonomous vehicle architectures. In developing functional safety that addresses hardware random failures and systematic failures, it is also crucial to consider cybersecurity and safety of intended functionality (SOTIF). This talk will cover an overview of the IEEE P2851 family of standards, which aim to provide an exchangeable and interoperable format for safety analysis and safety verification activities at IP, SoC and system levels. The standard addresses interoperability challenges of dependable systems covering functional safety, SOTIF, cybersecurity and other characteristics such as reliability, maintainability and real time.
Lei Wu is a Digital Design Manager in Embedded Processing Group in Texas Instruments and has been with TI since 2007. Her interests span automotive design quality enablement, test cost reduction and DFT execution optimizations. Lei received her Ph. D. in Computer Engineering from Texas A&M University in 2007.
Rajagopal works for TI’s Processor Design group on Physical Design, Static Timing Analysis and Design for Test on Automotive and Industrial Processors. He has held various positions in his prior work including designing large Custom ASICs for Wireless Infrastructure and Networking products, Mixed-signal designs for Automotive Radar and Wireless basestation, defining timing and power solutions in advanced technology nodes, developing internal EDA tools and methodology.
His current interests include system solutions, high speed peripherals, and power-performance co-optimization.
In automotive industry, where lives are at stake, defective parts are not an option. Automotive devices set DPPM goal in single digits, even “zero”, which drives the requirement of very high test coverage. Recent TI automotive SoCs have significant coverage contribution from 3rd party Highspeed IOs, some estimated as much as 8% of overall SoC fault count is from HS IOs. Due to high performance and mixed-signal nature, HS IO has a combination of digital scan, digital non-scan and mixed-signal “model” components. Integrating 3rd party HS IOs (PHYs) presents great challenges to achieve high test coverage and meet very low DPPM requirement in automotive devices. In this presentation we address challenges in testing 3P HS IOs (PHYs), variations in 3P implementations and presents solutions to improve test coverage on HS IOs (PHYs) and fix timing model to meet test requirement. The talk also exhibits how we have influenced the 3rd party ecosystem with automotive careabouts.