Janusz Rajski, vice president of Engineering, Mentor, A Siemens Business, joined Mentor Graphics in 1995. During his tenure at Mentor he has built a strong R&D organization with focus on innovative Design for Test technologies and collaboration with leading semiconductor companies. Under his leadership the team has developed a number of revolutionary industry-first products: TestKompress, the first commercial test compression product, and Cell-Aware Test technology which provides unprecedented test quality and accuracy of diagnosis. Both are increasingly important for smaller technology nodes and automotive applications. He has published more than 240 IEEE research papers and is co-inventor of more than 100 US and corresponding number of international patents. His papers and patents have over 12,000 citations and won many prestigious awards, including two Donald Pederson best paper awards for papers published in the IEEE Transactions on CAD papers.
A Lifetime Fellow of the IEEE, he holds a Master of Science degree in electrical engineering from the Gdańsk University of Technology and a Ph.D. degree in electrical engineering as well as an honorary doctorate from the Poznań University of Technology. In 2003, he was awarded the prestigious title of “Professor of Science” by the President of Poland. In 2009 he received the Stephen Swerling Innovation Award from Mentor Graphics “for his breakthrough innovation, TestKompress, and his many contributions to revitalizing Mentor’s DFT business to its current position as #1 test business in EDA”. In 2018, Rajski received the Siemen’s Lifetime Achievement Award for his extensive contributions to DFT.
Rohit Kapur is a Distinguished Engineer at Cadence in the area of Test Automation. Rohit is an IEEE Fellow and has a Ph.D. from the University of Texas at Austin specializing in IC Testing. Rohit has chaired the IEEE 1450.6 standard that defines the Core Test Language which is currently being used in the major EDA solutions. Rohit has served on the board of governors of Computer Society, he has chaired the standards activities for IEEE in the test area for over 10 years and currently serves on the board of IEEE Computer Magazine leading the publications in Computing Practices. Rohit is the author of a book and has over 100 publications and 40 patents in the area of IC test.
Kaushik Narayanun is a Senior Director & Head of DFX Engineering at NVIDIA Corporation. He received a B.E.(Hons) in Electronics & Communication Engineering from University of Madras, an M.S. in Computer Engineering from University of California, Santa Cruz and an M.B.A.(Hons) from INSEAD, France. He has spent his career architecting and productizing DFX solutions for industry’s leading SOCs and GPUs. He has also helped solve challenging silicon manufacturing problems through multiple process node transitions including latest FinFET technologies. Mr. Narayanun is passionate about developing groundbreaking methodologies for system level test architectures and designs to deliver on quality and cost metrics. In the recent past, he has focused on reframing the needs of and leveraging the architectures in semiconductor test for solving imminent needs in Functional Safety, Resiliency and Reliability for new markets like Automotive, AI & Cloud.
- Vice President – Test Automation Group
- Head of the Test Business Unit with end to end focus on R&D, Marketing, Solution and Application
- Prior to Synopsys was with Intel PEG as VP-Test for DFT, Automotive and FuSa related central engineering methodology and Architecture.
- At Nvidia was Sr Director of VLSI design and test group for all product ranging from GPU, CPU, SOC etc. Drove the ISO 26262 Automotive In system test solutions and process and methodology for Nvidia.
- Worked at Sun Microsystem on Microprocessor design/test, CAD, VLSI circuits and network Asics.
- 23+ years of experience in Design, Test, Automation, Software and silicon engineering
Michael Campbell is Senior Vice President of Engineering for QUALCOMM CDMA Technologies, responsible for QCT Product and Test Engineering, Test Automation and Failure Analysis. Mike joined QCT in 1996 as a Staff Engineer/Manager and since then Mike has led a diverse set of responsibility at Qualcomm, including, FA, Quality, Design Automation, Yield optimization, Product Engineering, Test Engineering, and Foundry semiconductor analysis.
At Qualcomm, Mike has helped bring up and drive the design office in Bangalore, the Design and test development center in Singapore and a development facility in Taiwan. In his current role, he is working to improve process bring up at our foundry partners, and 2nd source optimization. He is also working to optimize design processes in new process nodes to enable improved time to yield on Qualcomm’s products while enable faster time to market, at lower cost.
Prior to joining QUALCOMM, Mike was an engineer and manager at several semiconductor companies, including Mostek, INMOS and Honeywell. He holds a BSEE & CE from Clarkson University.