25+ years of experience in Design, Test, Automation, Software and silicon engineering
Silicon Lifecycle Management (SLM) is changing the way the semiconductor community thinks about device performance, health and predictability. At each lifecycle stage, there is a growing opportunity for meaningful data to be generated and analysed. This deep insight across the design, manufacturing, test and in-field deployment phases will enable decision making, helping to improve yield, quality and reliability, whilst also shortening product time to market. Once silicon is deployed into systems in the field, analytics can be conducted on large sample data sets, across entire product ranges or fleets, providing visibility of longer-term trends to enhance performance optimization and resilience.
The lifecycle management of semiconductor products is changing the way the chip industry thinks about device performance, health and predictability. At each lifecycle stage, there is a growing opportunity for meaningful data to be generated and analysed. This deep insight across the design, manufacturing, test and in-field deployment phases will enable decision making, helping to improve yield, quality and reliability, whilst also shortening product time to market. Once silicon is deployed into systems in the field, analytics can be conducted on large sample data sets, across entire product ranges or fleets, providing visibility of longer-term trends to enhance performance optimization and resilience.
Opportunities gather pace for developing new, insightful sensing and analytics technologies that resonate with customer and partner ecosystems alike. Silicon Lifecycle Management is one of the most exciting areas of growth for the semiconductor industry and has emerged as a key area of focus for Synopsys. The nexus of test with lifecycle management is an exciting area of development and will create significant value and growth for this audience in the coming years.
Jeff Rearick is a Senior Fellow with Advanced Micro Devices, where he has worked for 15 years and leads the DFT Strategy team. Prior to joining AMD, Jeff worked at HP/Agilent for 22 years on DFT methodology and implementation for a variety of microprocessor and networking chips. He served as Editor for the IEEE 1687 standard, currently holds that same role for both the IEEE P1687.1 and P1687.2 Working Groups, and is a member of the P2427 Working Group; he was a founder of all four of those efforts. He was also a member of the IEEE 1149.6 working group and co-authored the first publication of an implementation of that standard. He has published dozens of other technical papers and presentations, holds over 40 patents, and is an active member of the Test Technology Standards Committee as well as the program committees of the International Test Conference and the European Test Symposium. He earned B.S.E.E and M.S.E.E degrees from Purdue University and the University of Illinois, respectively, and was the recipient of the Bob Madge Innovation Award in 2016 and the Hans Karlsson Award from the IEEE Computer Society in 2018.
As we enter the “More than Moore” era of semiconductor integration, chiplets have emerged as a leading technology vector and show great promise as a platform for many products. As with most new technologies, they also bring with them many new challenges, including several for the test community. This presentation will give an overview of the motivation behind and the benefits of chiplet-based architectures, discuss some specific challenges associated with testing chiplets and chiplet-based systems, and suggest some avenues that the test community can take to address these issues.
John Carulli is the Director of the PostFab Test Development Center at GLOBALFOUNDRIES. He joined GF in 2014, based in Malta, NY. He previously had 21 years at Texas Instruments where he was a Distinguished Member of the Technical Staff. John has held technical and management positions across product lines, technology development, and operations. His research interests include product reliability, outlier analysis, machine learning, performance modeling, logic diagnosis, and security.
John holds 8 US Patents. He has over 50 publications in the areas of reliability, test, security, and process development. He is co-recipient of two Best Paper Awards and two Best Paper Nominations working in close collaboration with university partners. John serves on the organizing or program committees of several conferences including the International Test Conference, VLSI Test Symposium, and European Test Symposium. He is a Senior Member of IEEE. He received his B.S.E.E. and M.S.E.E. degrees from the University of Vermont in Burlington, VT.
Design-for-Testability is the foundation of chip design in every market. From large digital System-on-Chip to relatively smaller integrated circuits in analog, mixed-signal and RF, a successful end-product requires early collaborative design consideration. Our manufacturing partners rely on this infrastructure to drive yield, quality, delivery, and cost. Our end-customers additionally rely on these capabilities to have confidence in product reliability, safety and security. In this presentation we will discuss some examples of how your “DFT” efforts are leveraged in the silicon life cycle.
Phil is a Distinguished Technical Staff Member in Broadcom’s ASIC Product Division. He is responsible for driving quality & test improvements for 7nm, 5nm and 3nm products. He has worked in IC testing for 38 years — including for IBM & GlobalFoundries — and has over 25 patents. Phil has also organized the “Industry Test Challenges” workshop for over 20 years — and is on the Program Committee for a number of conferences and industry groups. Phil has a PhD from Carnegie Mellon University.
Advanced technology products are causing discontinuities in how we Test ICs. The following are some of the challenges we are facing. I’ll summarize the challenges — and provide some practical solutions to address these challenges.
Vivek Chickermane is a Distinguished Engineer at Cadence Design Systems where he is also a Senior Group Director for R&D in the Modus DFT Software group which is a part of Cadence’s Digital Systems Group. His professional responsibilities include design and productization of in-system DFT features that are used in high quality and safety-critical applications. He has been involved in the frontlines of productizing key DFT features such as OPMISR Compression technology in 2001, IEEE 1149.6 (AC-JTAG) in 2004, IEEE 1500 Core Test Wrapper synthesis in 2005, development of the first EDA Common Power Format (CPF) in 2008 which could be used by all tools in an RTL to GDS2 including power-aware test. More recently he and his team have productized 3D IC DFT, Hierarchical Test Compression using pattern migration, IEEE 1687 (iJTAG) and physically-aware 2D Compression to reduce the cost of test. Prior to Cadence, Dr Chickermane was at IBM’s Microelectronics Division where he led the development of the first DFT Synthesis tool in their BooleDozer Synthesis tool which was used in the front-end of their vector-less ASIC sign-off flow.
Dr Chickermane has published more than 85 technical refereed technical articles and papers and is also a co-inventor of more than 55 US patents awarded or pending. He serves on several IEEE conference and standards committees and is currently an Associate Editor of IEEE Design & Test. He received his B.Tech in Electrical Engineering from Indian Institute of Technology, New Delhi and his M.S and Ph.D degrees in Computer Engineering from the Univ. of Illinois at Urbana-Champaign.
The city of Bengaluru aka Bangalore has played a prominent role in elevating locally developed technology to world class status. With its long history of innovation in aerospace, electronics, IT, telecommunications, machine tooling and many others, Bangalore is the de-facto Tech Capital of India. Inspired by its long historical association with innovation this presentation will provide some background on the long history of efforts to build multi-chip modules which is also synonymous with heterogenous integration, 2.5D or 3D packaging. In particular we will discuss the challenges in the EDA space where efforts to scale solutions that work really well in the flat world have faced headwinds in moving to the vertical dimension. To make 3D packaging practical requires automation that spans the widely distributed microelectronics supply chain.
Thankfully we can dip into the reservoirs of 5 decades of technical contributions in design and test of multi-chip systems and take advantage of modern computational methods and design flows to make 3D integration technically feasible and cost efficient. This talk will provide some insights into what it will take to elevate the best practices of current EDA tools to 3D success.