T1: Machine Learning in Test

Abstract

In this tutorial, we will start by covering the basics of machine learning. We will proceed to give a brief overview of the new and exciting field of deep learning. We will show how easy it is to try using machine learning and deep learning, thanks to powerful, free libraries. After offering the required background in machine learning, we will review several important papers in the field of DFT, diagnosis, yield learning, and root cause analysis, which use machine learning algorithms for solving various problems. Finally, we will propose future research directions in the area of testing, where we think machine learning (especially deep learning) can make a big impact.

Bio of Presenters

Dr. Yu Huang

Dr. Yu Huang is a Principal Engineer in the Silicon Test Systems Division of Mentor, A Siemens Business. His research interests include VLSI SoC testing, ATPG, compression and diagnosis. He holds 26 US patents and has 4 more patents pending. He has published more than 100 papers in leading IEEE Journals, conferences and workshops. He is a senior member of the IEEE. He has served as technical program committee member for DAC, ITC, ATS, ETS, ASPDAC, NATW and other conferences and workshops in the testing area. He received a Ph.D. from the University of Iowa in 2002.

Gaurav Veda

Gaurav Veda received a BTech in Computer Science from IIT Kanpur, India in 2005. He received an MS from the Computer Science Department at Carnegie Mellon University. At CMU he was a graduate student from 2005-2010, and did core machine learning research. He left the PhD program in 2010 to join Tower Research Capital, where he did research, development, and deployment of machine learning based trading strategies. He moved to Portland, Oregon in 2015 and joined a startup hedge fund. He joined Mentor, a Siemens Business in itc_archives/2017 as a Machine Learning Research Engineer, to use machine learning in the test domain.

T2: Automotive Reliability & Test Strategies

Abstract

Given today’s fast growing automotive semiconductor industry, this tutorial will discuss the implications of automotive test, reliability and functional safety on all aspects of the SOC lifecycle, while accelerating time to market for automotive SOCs. The SOC lifecycle stages will include design, silicon bring-up, volume production, and particularly in-system test. Today’s automotive safety critical chips need multiple in-system self-test modes, such as power-on self-test and repair, periodic in-field self-test during mission mode, advanced error correction solutions, etc. This tutorial will analyze these specific in-system test modes and the discuss the benefits of using ISO 26262 including its 2nd edition (to be published in 2018), in order to ensure that standardized functional safety requirements are met.

Bio of Presenters

Yervant Zorian

Chief Architect and Fellow at Synopsys, President of Synopsys Armenia Dr. Zorian is a Chief Architect and Fellow at Synopsys, as well as President of Synopsys Armenia. Formerly, he was Vice President and Chief Scientist of Virage Logic, Chief Technologist at LogicVision, and a Distinguished Member of Technical Staff AT&T Bell Laboratories. He is currently the President of IEEE Test Technology Technical Council (TTTC), the founder and chair of the IEEE 1500 Standardization Working Group, the Editor-in-Chief Emeritus of the IEEE Design and Test of Computers and an Adjunct Professor at University of British Columbia. He served on the Board of Governors of Computer Society and CEDA, was the Vice President of IEEE Computer Society, and the General Chair of the 50th Design Automation Conference (DAC) and several other symposia and workshops.

Dr. Zorian holds 36 US patents, has authored four books, published over 350 refereed papers and received numerous best paper awards. A Fellow of the IEEE since 1999, Dr. Zorian was the 2005 recipient of the prestigious Industrial Pioneer Award for his contribution to BIST, and the 2006 recipient of the IEEE Hans Karlsson Award for diplomacy. He received the IEEE Distinguished Services Award for leading the TTTC, the IEEE Meritorious Award for outstanding contributions to EDA, and in 2014, the Republic of Armenia's National Medal of Science. He received an MS degree in Computer Engineering from University of Southern California, a PhD in Electrical Engineering from McGill University, and an MBA from Wharton School of Business, University of Pennsylvania.

Riccardo Mariani

Intel Fellow and Chief Functional Safety Technologist Riccardo Mariani is widely recognized as an expert in functional safety and integrated ircuit reliability. In his current role as chief functional safety technologist at Intel Corporation, he oversees strategies and technologies for IoT applications that require functional safety, high reliability and performance, such as autonomous driving, transportation and industrial systems. Mariani spent the bulk of his career as CTO of Yogitech, an industry leader in functional safety technologies. Before co-founding the Italian company in 2000, he was technical director at Aurelia Microelettronica, where his responsibilities included leading high-reliability topics in projects with CERN in Geneva. A prolific author and respected inventor in the functional safety field, Mariani has contributed to multiple industry standards efforts throughout his career, including leading the ISO 26262-11 part specific to semiconductors. He has also won the SGS-Thomson Award and the Enrico Denoth Award for his engineering achievements. He holds a bachelor’s degree in electronic engineering and a Ph.D. in microelectronics from the University of Pisa in Italy.

T3: Test Access Mechanism (TAM) for Advanced SoCs

Abstract

The increasing complexity and integration of IPs on modern SOCs are creating new challenges for test access mechanisms (TAM) on these devices. Direct access of the IPs for test is not only prohibitive in terms of design cost, but also adds up to the cost of testing the device. For the large SoCs, a scalable TAM is required that can provide the mechanism to access multiple and replicated digital cores, memory arrays as well as Analog and Mixed signal IPs on the chip. The architectures should also provide sufficient bandwidth as well so as to be able to reduce the overall time required to test the chip. In this tutorial we will cover major architectures available for designing TAM, suitable for devices ranging across the smallest IoT device to large servers. In addition, we will give an overview of the standards and best practices and the analysis for coming up with a robust TAM infrastructure for different kinds of SOC. The DFT practitioner will get a holistic overview of TAM architecture, methodology and best-practices.

Bio of Presenters

Jais Abraham

Jais Abraham is Director, Engineering at Qualcomm India Private Limited, where he focuses on the Design-For-Test methodology. After graduating in Electronics Engineering from IIT- Chennai, he worked at Texas Instruments, AMD and most recently at Intel, looking into the DFT of various classes of products ranging from extremely cost-sensitive products to high speed processors and also products with stringent quality requirements. Jais has co-authored multiple technical papers in various conferences and is a co-inventor of 6 patents.

Punit kishore

Punit kishore received his B.tech (EE) from IIT kanpur in 2004. He is currently Engineer, Principal/Mgr at Qualcomm India Private Limited. Before that he has worked for Texas Instruments, NVIDIA and Intel. Punit has worked in different aspects of DFT like ATPG, diagnosis, mixed signal DFT, memory testing and repair. He has 3 US patents.

Shamitha Rao

Shamitha Rao received her Bachelors in Engineering in Electronics Engineering from University BDT College of Engineering, Davanagere. She is currently an Applications Engineer for the DFT products at Mentor Graphics, Bangalore. Before taking up her role with Mentor Graphics, she worked in design and implementation domains at various companies like Insilica Semiconductors, ST Microelectronics, Wipro Technologies etc. She has co-authored 3 technical papers at various conference proceedings.

Srijesh Parambath

Srijesh Parambath has been associated with Mentor Graphics since 2008 and is managing the DFT India Technical team out of Bangalore. Prior to Mentor Graphics, he was with CoreEL Technologies owning functional responsibilities of Design, Applications and Architecture definition in the areas of VLSI & Hardware Engineering. A technologist with 15 years of experience in EDA, ASIC & System design domains, Srijesh has a Bachelor degree in Electronics & Communications from Bangalore University.

T4: Are System Level Tests Unavoidable for High End Processors?

Abstract

This tutorial aims at understanding the increasing use of system level tests to screen smartphone and notebook processors for manufacturing defects by taking an in-depth look at the limitations of state-of-the-art scan test methodology.

ICs and SOCs have long been tested using low cost scan based structural tests to screen out defects post manufacturing. Recently, the new cell-aware IC test methodology has received much publicity because of its success in screening significant defectivity missed by tests generated using the traditional stuck-at and transition delay fault (TDF) fault models. However, these tests, even when further supplemented by additional tests generated by other new fault models such as gate exhaustive, still appear unable to detect many defects in the current generation of microprocessor and smartphone SOCs. Today, these applications are increasing relying on an additional test insertion during the test and packaging flow, incorporating expensive system level tests (SLTs), as a final screen for defective devices. Mobile phone SOCs, for example, are temporarily mounted on specially designed, reusable, phone test boards, and a broad range of functional applications are run over a period of 10 to 15 minutes as a final check of full functionality. Similar SLT testing is also performed on many laptop and notebook processor SOCs. However, while these system level tests do screen out a significant number of defective parts, they do not provide a complete test in themselves. Such functional tests have long been known to miss many manufacturing defects reliably detected by traditional scan tests. This rules out any possibility of eliminating conventional structural testing when SLTs are used. Consequently, industry’s effort towards reducing test costs are focused on improving traditional scan based structural tests to minimize the need for the expensive SLTs where possible. SLTs are often indispensable early in production when yields are low; the goal typically is to reduce use of these tests as the process matures and stabilizes. This requires a good understanding of the classes of defects that are uniquely detected by SLTs so that structural tests may be enhanced to cover these test escapes.

This tutorial categorizes the failures detected by the final system level tests into four broad classes: (1) Hard defects (shorts and opens) that escape scan structural tests. (2) Latent defects (smaller manufacturing flaws that result in “burn-in” or early life failures over time) that do not manifest as functional defects during the initial scan test but are stressed to failure during the relatively long SLTs. (3) Failures due to delay defects and process related timing marginalities that are missed by the scan delay tests. (4) False alarms that incorrectly flag a good part as faulty. State-of-the-art structural test methodologies for each of these “fault” classes will be discussed in depth to understand the specific type of “defects” that can escape, and what additional tests may be needed to improve defect coverage. We particularly focus on classes (1) and (3) as described below, because they appear to be the primary drivers of the need for system level tests.

Bio of Presenters

Dr. Adit D. Singh

Dr. Adit D. Singh is James B. Davis Distinguished Professor of Electrical and Computer Engineering at Auburn University. Before joining Auburn in 1991, he served on the faculty at the University of Massachusetts in Amherst, and Virginia Tech in Blacksburg. He has held several visiting positions during sabbaticals, including at the University of Tokyo in Japan, the Universities of Freiburg and Potsdam in Germany, the Indian Institutes of Technology, and as Fulbright Awardee at the University Polytechnic of Catalonia in Barcelona, Spain. He has also conducted over 70 tutorials and short courses at conferences, universities and industry worldwide. His technical interests span all aspects of VLSI technology, in particular integrated circuit test and reliability. He has published over two hundred and fifty research papers and holds international patents that have been licensed to industry. He is particularly recognized for his pioneering contributions to statistical methods in test and adaptive testing. He has served as a consultant to many major semiconductor, test and EDA companies around the world, including as an expert witness on patent litigation cases. He has had leadership roles as General Chair/Co-Chair/Program Chair for dozens of international VLSI design and test conferences. Most recently he was Program Co-Chair for the 2014 International Conference on VLSI Design, and Program Chair for the 2015 Asian Test Symposium. He also served on the editorial boards of several journals, including IEEE Design and Test, and on the Steering and Program Committees of many of the major IEEE international test and design automation conferences. He served two terms (2007-11) as Chair of the IEEE Test Technology Technical Council (TTTC), and (2011-15) on the Board of Governors of the IEEE Council on Design Automation (CEDA). Professor Singh was elected Fellow of IEEE in 2002. He is Golden Core member of the IEEE Computer Society.

T5: Recent Trends in Modelling and Simulation of Defects in Analog Circuits and their Applications

Abstract

The amount and complexity of Analog and mixed-signal (AMS) and RF components in SoCs have considerably increased with SOCs increasingly designed for Automotive, Industrial and Embedded Processing applications. Big SOCs are often dominated by such components, which in turn increase the overall test complexity, test time, time required for silicon debug and characterization, and adversely affect achievable test quality. There has been tremendous improvement in testing methods and detecting defects, modeled as faults, in digital circuits over the last 20 years using proven techniques, such as stuck-at faults and scan based testing. However, there is no industry standard analog fault model till date for AMS circuits. Several IC design companies started building their own analog fault models integrated either with their in-built or third party simulators. Even after such efforts targeted towards analog fault simulation, the number of test escapes, also known as Defective Parts per Million (DPPM), has not reduced beyond a certain level since 2012.

There were some techniques proposed and implemented by various Industries and Academia, and one or more of them are also in use by few mixed-signal IC design companies. Techniques such as multisite testing have been applied with success to reduce test time by sharing instruments among multiple Devices under Test (DUT). However, they are reaching their economical limitations and have agreed to novel directions to be explored. Methods such as Random sampling, Likelihood-weighted random sampling (LWRS) are currently in use, though they potentially exercise only a small subset of all possible defects.

Bio of Presenters

Vijay Kumar Sankaran

Vijay Kumar Sankaran is a Principal Applications Engineer at Cadence Design Systems (India) Pvt. Ltd., Bangalore with more than 10 years of experience in the field of Analog and Mixed Signal SoC Verification and Application support. Vijay is primarily responsible for supporting IC designers and verification engineers by driving AMS design & verification methodologies, including low power mixed-signal verification, mixed-signal functional safety analysis and mixed-signal fault simulations. Vijay holds B.E in Electronics and Communication Engineering from Anna University, Chennai and M.Tech. in Microelectronics from Birla Institute of Technology and Science, Pilani.

Lakshmanan Balasubramania

Lakshmanan Balasubramanian is an AMS Lead & Member, Group Technical Staff with Texas Instruments (India) Pvt. Ltd., Bengaluru, primarily responsible for AMS SoC design integration and verification aspects for the low power and connected microcontroller (MSP43x) SoC development. He has expertise of more than 17 years in various fields of VLSI such as analog & embedded power management design, custom low power digital design, AMS design & verification methodologies, and analog DFT technologies. Lakshmanan holds Bachelor of Science degree in Physics from University of Madras, Bachelor of Technology degree in Electronics Engineering from MIT, Anna University, Chennai, and a Master of Technology degree from IISc, Bangalore. He has published several conference and journal papers and 3 patents. He is a Senior member of IEEE, Member of the IET, Chartered Engineer (CEng) of Engineering Council UK, and currently an International Professional Registration Advisor (IPRA) / Professional Review Interviewer (PRI) with the IET. He is a member of the IEEE standards working groups on Analog test (P1687.2) & analog coverage (P2427).

Nadeem Husain Tehsildar

Nadeem Husain Tehsildar is a Design Engineer with Texas Instruments (India) Pvt. Ltd., Bangalore, primarily responsible for DMS & AMS co-simulation based verification of connected and low power MCU SoCs since 2015. He holds a BE degree from BVB college of Engineering and Technology, Hubli, & an M.Tech from MSRIT, Bangalore.

T6: Logic Encryption: A Design-for-Security Trust Methodology for Digital Integrated Circuits

Abstract

With the globalization of IC design flow, many fabless companies outsource the fabrication of their design to off-site foundries. As these foundries may not always be trusted, it results in security vulnerabilities and threats such as counterfeiting, IP piracy, reverse engineering, overbuilding, and insertion of Hardware Trojans. Logic encryption has emerged to be a potential solution to secure the design against these threats. It introduces obfuscation by inserting some extra hardware into a circuit to hide its functionality from unauthorized users. Correct functionality of an encrypted design depends upon the application of right keys, shared only with the authorized users. In the recent past, extensive efforts have been devoted to extracting the secret key of a logically encrypted design. At the same time, several countermeasures have also been proposed by the research community to thwart different state-of-the-art attacks on logic encryption. Although several countermeasures can prevent different attacks separately, however, the contradictory requirements of these countermeasures inhibit the researchers from coming up with a single solution which can thwart all the state-of-the-art attacks. As the vulnerability to at least one attack is sufficient enough to compromise the secret key, one cannot claim a logic encryption technique is secure until it is capable of preventing all the contemporary attacks. Therefore, it has become extremely challenging to devise a single logic encryption technique which can thwart all the state-of-the art attacks and simultaneously fulfills other fundamental criteria like high output corruption for wrong keys, low design overhead, and low implementation complexity.

Bio of Presenters

Santanu Chattopadhyay

Santanu Chattopadhyay received the B.E. degree in computer science and technology from Calcutta University, Kolkata, India, in 1990, the M.Tech. degree in computer and information technology and the Ph.D. degree in computer science and engineering from the IIT Kharagpur, Kharagpur, India, in 1992 and 1996,respectively. He is currently a Professor with the Department of Electronics and Electrical Communication Engineering at IIT Kharagpur. He has published more than 150 technical papers in peer-reviewed journals and conferences. His current research interests include digital circuit design, testing and diagnosis, hardware security, network-on-chip design and test, and low-power circuit design and test.

Rajit Karmakar

Rajit Karmakar received his MS degree in Microelectronics and VLSI from Indian Institute of Technology, Kharagpur, India, in 2015. He is presently a PhD student in the Department of Electronics and Electrical Communication Engineering, Indian Institute of Technology, Kharagpur, India. His current research interests include Hardware Security and VLSI Testing. He has published several research papers in reputed International journals and conferences. He is a student member of IEEE.