Dr. Yervant Zorian

Chief Architect and Fellow at Synopsys, President of Synopsys Armenia

Keynote Title:

Infrastructure IP for Today’s Automotive SOCs

Abstract:

Given today’s fast growing automotive semiconductor industry, this keynote will discuss the implications of automotive test, reliability, safety and security requirements on Infrastructure IP needed for all aspects of the SOC lifecycle: design, silicon bring-up, volume production, and particularly in- system functional safety. Today’s automotive Infrastructure IP is needed for multiple in-system self-test modes, such as power-on self-test and repair, periodic in-field self-test, advanced error correction, etc. This keynote will cover these specific in-system modes and the benefits of selecting ISO 26262 certified solutions to ensure standardized quality, safety and security requirements, while accelerating time to market for today’s automotive SOCs.

Bio:

Dr. Yervant Zorian is a Chief Architect and Fellow at Synopsys, as well as President of Synopsys Armenia. Formerly, he was Vice President and Chief Scientist of Virage Logic, Chief Technologist at LogicVision, and a Distinguished Member of Technical Staff AT&T Bell Laboratories. He is currently the President of IEEE Test Technology Technical Council (TTTC), the founder and chair of the IEEE 1500 Standardization Working Group, the Editor-in-Chief Emeritus of the IEEE Design and Test of Computers and an Adjunct Professor at University of British Columbia. He served on the Board of Governors of Computer Society and CEDA, was the Vice President of IEEE Computer Society, and the General Chair of the 50th Design Automation Conference (DAC) and several other symposia and workshops. Dr. Zorian holds 35 US patents, has authored four books, published over 350 refereed papers and received numerous best paper awards. A Fellow of the IEEE since 1999, Dr. Zorian was the 2005 recipient of the prestigious Industrial Pioneer Award for his contribution to BIST, and the 2006 recipient of the IEEE Hans Karlsson Award for diplomacy. He received the IEEE Distinguished Services Award for leading the TTTC, the IEEE Meritorious Award for outstanding contributions to EDA, and in 2014, the Republic of Armenia's National Medal of Science. He received an MS degree in Computer Engineering from University of Southern California, a PhD in Electrical Engineering from McGill University, and an MBA from Wharton School of Business, University of Pennsylvania.

P. Raja Manickam

Founder & CEO, Tessolve

Keynote Title:

Testing in Always on Era

Abstract:

Electronic systems in today’s always connected world have become central part of all aspects of public, private and social life. This requires the systems to be always available. These systems also are being used in very specialized functions. Almost all of these systems have a SoC a lot of them build for specific functions. Most of these SOCs are tested Structural Test, Functional Test, Characterization test, Burnin test and other test. These tests are exhaustive test to cover all components on the test. These test are mostly Bottom up test. Since SoCs are today subjected to specialized functions can we rethink test to ensure that all test are applied with the end use in mind. Some of these methods may require additional test to meet quality requirement of end use but in some cases would mean test cost saving. A high level view of such a flow will be presented with industry ecosystem, if it can provide any advantages.

Bio:

Raja Manickam founded Tessolve in 2003 with a vision to create a leading productization company delivering high volume manufactured products from physical silicon. He brings a unique mix of experience encompassing the entire chip development process, from managing product lines, running a manufacturing site and building up start-ups. This experience allowed him to build Tessolve to bridge the gaps he saw in the development cycle of silicon engineering. Starting his career as a test engineer in Texas Instruments he moved on to Fairchild, National Semiconductor, DTS and Viko test labs. He was also involved in the early startup of STATS and UTAC. In his vibrant 30 year career, he held engineering, product line, sales and marketing responsibilities in his 30-year career.

Nilanjan Mukherjee

Engineering Director, Tessent, Mentor – A Siemens Business.

Keynote Title:

Self-Driving Cars – how they are pushing the boundaries of IC Testing.

Abstract:

The design of self-driving cars is rapidly increasing the electronic content within automotive vehicles. The more the built-in intelligence, the higher the processing power required. The increasing complexity of ICs being deployed for safety-critical applications along with advanced technology nodes used for manufacturing poses serious challenges towards guaranteeing high quality and reliability. This talk will cover some of the test methodologies being deployed for automotive ICs covering digital logic, memories, and analog mixed-signal logic. Additionally, it will also highlight system test solutions being explored for key-on, key-off, and online monitoring throughout the life-span of such devices.

Bio:

Nilanjan Mukherjee received a B.Tech.(Hons) degree in Electronics & Communication Engineering from IIT, Kharagpur, and a Ph.D. degree from McGill University, Canada. Dr. Mukherjee is currently the Engineering Director in the Design-to-Silicon division at Mentor Graphics. At Mentor Graphics, he was a co-inventor of the EDT technology, VersaPoint Test Points, and Low Power Logic BIST, and was a lead developer for TestKompress, which is the leading test compression tool in the industry today. Prior to joining Mentor Graphics, he worked at Lucent Bell Laboratories in New Jersey.
Dr. Mukherjee has co-authored more than 75 technical papers at various conference proceedings and archival journals. He is a co-inventor of 47 US patents and several international patents. He has received numerous Best Paper awards including the Most Significant Paper Award at ITC 2012, the Best Paper Award at VLSI Design in 2009, the Donald O. Pederson Outstanding Paper Award from the IEEE Circuits and Systems Society in 2006, the Teruhiko Yamada Memorial Best Student Paper Award at ATS 2001, and the Best Paper Award at VTS 1995. Dr. Mukherjee has served on the program committee for various technical conferences and workshops. He has represented Mentor Graphics at the Semiconductor Research Organization (SRC), at the International Technology Roadmap for Semiconductors (ITRS), and as a panelist for National Science Foundation (NSF). Dr. Mukherjee has given several tutorials at DAC, ITC, and VLSI Design conferences, offered short term courses on DFT, and has given talks at various conferences and company sponsored events.

Ravi Mahajan

Fellow, Intel

Keynote Title:

Directions in Advanced Packaging Technology

Abstract:

Heterogeneous Integration (HI) of disparate computing and communications functions is a key enabler of performance in micro-electronic systems. HI is crucially enabled by advanced packaging since packages are an optimal HI platform. This talk will address the role of packaging in enabling HI and will focus primarily on the technology evolution of package interconnect densities. It will show how packaging has evolved to provide increased interconnect density and how the different technology solutions available today meet the demands of diverse markets. Key high-end technologies such as EMIB and the silicon interposer will be discussed in this context. The talk will also touch on the evolving future challenges in interconnect density scaling. In addition to interconnect scaling, this talk will also briefly discuss challenges and opportunities in key areas such as power management, high speed IO, thermal management and test.

Bio:

Ravi Mahajan is an Intel Fellow and the Co-director of Pathfinding and Assembly and Packaging technologies for 7nm silicon and beyond in the Technology and Manufacturing Group at Intel Corporation. He has led efforts to define and set strategic direction for package architecture, technologies and assembly processes at Intel since 2000, spanning 90nm, 65nm, 45nm, 32nm, 22nm and 7nm silicon.
Ravi holds more than 40 patents (including the original patent for a silicon bridge that became the foundation for Intel’s Embedded Multi-Die Interconnect Bridge technology) and has written several book chapters and more than 30 papers on topics related to his area of expertise.
Ravi joined Intel in 1992 after earning a bachelor’s degree from Bombay University, a master’s degree from the University of Houston, and a Ph.D. from Lehigh University, all in mechanical engineering. His contributioans during his Intel career have earned him numerous industry honors, including the SRC’s 2015 Mahboob Khan Outstanding Industry Liaison Award, the 2016 THERMI award from SEMITHERM and the 2016 Allan Kraus Thermal Management Medal from the American Society of Mechanical Engineers. He has been nominated as an IEEE CPMT Distinguished Lecturer. He is one of the founding editors for the Intel Assembly and Test Technology Journal (IATTJ) and currently VP of Publications & Managing Editor-in-Chief of the IEEE Transactions of the CPMT. Additionally, he has been long associated with ASME’s InterPACK conference and was Conference Co-Chair of the itc_archives/2017 Conference. Ravi is a Fellow of two leading societies, ASME and IEEE.