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Tutorial Program
| ITC India 2024 Tutorials | |||
|---|---|---|---|
| LONG TUTORIALS | |||
|
TITLE |
Authors | Affiliation | |
| Optimal Scan Bandwidth Management and Structural Test Over High-Speed functional interfaces using Advanced Test Technologies | Mohan Selvam, Pooja Vishwanath, Greeshma Jayakumar and Sri Ganta | Mediatek, Synopsys | |
| Functional Safety Readiness: Requirements in Design, Test and Application | Prasanth Viswanathan Pillai and Rubin Parekhji | Texas Instruments | |
| Architecture & Methodology for DFT of Low Power SoCs | Jais Abraham, Palkesh Jain, Subhadip Kundu and Nikhil Patil | Qualcomm | |
| ITC India 2024 Tutorials | |||
|---|---|---|---|
| SHORT TUTORIALS | |||
|
TITLE |
Authors | Affiliation | |
| Synchronous Interface Test Challenges for Complex ASIC, Practical Solutions for At-Speed Test | Veerabhadrarao Vasa and Vevekanenda G | ||
| Addressing Test, Safety and Security for Connected Automotive IC’s | Lee Harrison | Siemens EDA | |
| Ensuring robust RTL for DFT: Comprehensive verification strategy | Parth Kadiya, Piyushkumar Chaniyara, Mahipal Reddy, Satish Sajjanar and Pervez Garg | Texas Instruments | |
| DFT Designer’s Nightmare in the Nanometer Age | Ankush Srivastava and Kamlesh Pandey | Qualcomm | |
| Fault Modeling in Digital Integrated Circuits: How It Influences ATPG and DfT | Bhargab B. Bhattacharya and Susmita Sur-Kolay | Indian Statistical Institute, Kolkata | |
| Effective Low-Cost Strategies for Detecting Recycled Integrated circuits | Ujjwal Guin | Auburn University | |
| Sunday, July 23, 2023 | |||
|---|---|---|---|
| 8:00am-9:30am | REGISTRATIONS | ||
| TRACKS |
TRACK 1 Session Chair | Santosh Kumar |
TRACK 2 Session Chair | Dr. Subhadip Kundu, Krishnamachary Prathapuram |
TRACK 3 Session Chair | Prof. R. Jayagowri |
| HALL NAME | GRAND VICTORIA - A | GRAND VICTORIA - B | ARABICA & ROBUSTA |
|
9:30 am - 11:00 am (15 mins. Break) 11:15 am - 12:45 pm |
Seamless Integration of packetized scan with Advanced ATE equipment Lee Harrison (Siemens), Peter Orlando (Siemens), Michael Braun (Advantest) and Pudhukkarai Krishnan (Advantest) |
Design for Test – An indispensable slice of SOC (System on Chip) life cycle Shamitha Rao, Bala Krishna K (Intel) |
DFX beyond Compression Vijay Kumar K S, Kranthi Kandula, Leela Krishna Thota and Paras Chhabra (Synopsys) |
| 12:45pm-1:45pm | LUNCH BREAK | ||
|
1:45 pm - 3:15 pm (15 mins. Break) 3:30 pm - 5:00 pm |
Error Resilient AI System: Addressing Soft Errors, Security, Threats and Manufacturing Variability Effects Prof. Abhijit Chatterjee (Georgia Tech, USA) Guaranteeing quality in automotive EMC tests through in-house EMC test George Thottan, Rajesh Chauhan and Dilip Jain (Texas Instruments) |
Power Domains and Physical Synthesis – A DFT Perspective Sarthak Singhal, Subhasish Mukherjee, Dr. Krishna Chakravadhanula and Bharath Nandakumar (Cadence) Hierarchical and tile based DFT techniques for AI and Large SoCs Lee Harrison and Peter Orlando (Siemens) |
Hardware Security: A perspective towards Fault Analysis Vulnerabilities Prof. Bodhisatwa Mazumdar (IIT Indore) Power Aware DFT Karthik Natarajan, Likith Manchukonda, Manish Arora, Rahul Singhal and Greeshma Jayakumar (Synopsys) |
Long Tutorial 1
Title: Optimal Scan Bandwidth Management and Structural Test Over High-Speed functional interfaces using Advanced Test Technologies
Authors: Mohan Selvam, Greeshma Jayakumar, Sri Ganta and Pooja Vishwanath
Company: Mediatek, Synopsys
Tutorial Abstract:
In today’s complex semiconductor designs with advanced technology nodes, growing design sizes, and aggressive DPPM and reliability requirements, the number of test patterns and test data volume is exponentially increasing, and at the same time with limited or shrinking number of GPIOs on package, the test data bandwidth management and meeting desired test data throughput has been a major test challenge that directly impacts the test time, hence the test costs. In this joint tutorial, it will be discussed how MediaTek addressed these test challenges in the complex mobile SOCs using advanced test technologies, including Streaming Fabric (SF), Sequential Compression (SEQ), and High-Speed Access Test (HSAT) IP.
Mohanasundaram Selvam
Mohanasundaram Selvam is a Sr. DFT Manager in MediaTek with 18 years’ experience on DFT execution & management. He is leading DFT operations at MediaTek, Bangalore for Smartphone / TV / ASIC SOC’s. It includes defining DFT strategy and methodology for advanced process nodes to meet low power test requirements with better test cost.
Greeshma Jayakumar
Greeshma Jayakumar is an Application Engineering Manager in Synopsys Hardware Analytics and Test group, leading customer support for Synopsys TestMAX product line. With over 12 years in Design-For-Test (DFT), she specializes in test architecture, methodology, ATPG & silicon bring-up across diverse range of semiconductor designs. Prior to Synopsys she has been part of IBM & Global foundries where she worked on developing new test mythologies for advanced node designs. She holds a master’s degree in Electronics & Communication Engineering from College of Engineering Trivandrum.
Sri Ganta
Sri Raju Ganta is a Principal Product Manager in the EDA Group (EDAG) at Synopsys, managing Test family of products. Sri has over 20 years of experience in semiconductor test area, 10+ years in EDA at LogicVision and Siemens-EDA and 10+ years in ASIC/SOC product development at Broadcom and Qualcomm, where he held different technical and leadership roles. Prior to joining Synopsys, Sri was a Director of Business Development at Advantest, SLT division. Sri holds a MS in Engineering Management and a BTech. in Electronics and Communication Engineering.
Pooja Vishwanath
Pooja Vishwanath is a Senior Staff Engineer at Synopsys supporting TestMax set of products. With over 11 years of experience in the industry, Pooja has spent around 8 years within EDA at Siemens-EDA and now Synopsys. Prior to joining Synopsys, Pooja was an SoC Design Engineer at Intel. Pooja holds a bachelor’s degree in electrical and Electronics Engineering from B.M.S College of Engineering, Bangalore.
Long Tutorial 2
Title: Functional Safety Readiness: Requirements in Design, Test and Application
Authors: Prasanth Viswanathan Pillai and Rubin Parekhji
Company: Texas Instruments
Tutorial Abstract:
This tutorial covers, (and in the process demystifies), four aspects of semiconductor functional safety: (a) How are the well-known metrics for ASIL (automotive) and SIL (industrial) classification set. (b) How do these requirements drive the selection of the right set of detection and diagnostics mechanisms. (c) How is conformance to these classification levels assessed. (d) How are fault spaces and coverage numbers apportioned to different IC building blocks and higher level compositions at the system level. Industry examples highlighting how these requirements in design, test and application can drive readiness for functional safety will be discussed.
Rubin Parekhji
Rubin Parekhji has been with Texas Instruments, Bangalore, since 1996, where he has led and mentored DFT teams on various design and test technology projects across multiple product groups. More recently, he has been in the DLP and MCU Controller organisations at TI, working on low cost test methods and test entitlement targets with world-wide teams. He is a distinguished member of the technical staff. He has published regularly and delivered tutorials at leading conferences, has mentored a large number of students, has been a visiting faculty member for multiple academic terms, has been an active industry liaison for several industry projects, and has several issued patents. He has a Ph.D. from Indian Institute of Technology, Bombay, India.
Prasanth Viswanathan
Prasanth Viswanathan Pillai is working as Design Manager at Texas Instruments, Bangalore. He is a Senior Member of TI’s Technical Staff (SMTS). He is a member of United States Technical Advisory Group (USTAG) for ISO26262 which undertakes the development and revision of the automotive functional safety standard. His interests include architecture and design of accelerators, low-cost reliable systems and on-line test techniques. He has several publications, 9 granted patents and won three best paper awards including the best paper at ITC 2021. He holds a PhD degree from Indian Institute of Science, Bangalore.
Long Tutorial 3
Title: Architecture & Methodology for DFT of Low Power SoCs
Authors: Jais Abraham, Palkesh Jain, Subhadip Kundu and Nikhil Patil
Company: Qualcomm
Tutorial Abstract:
Low power SoCs impose unique challenges for DFT and for silicon testing. Tests must be created so as not to exceed the power budget of the design, while, at the same time not imposing excessive costs for testing under these constraints. In this tutorial, the challenges posed for DFT in low power designs like mobile processors and complex 5G modems will be covered. Specifically, an in-depth overview of thermal and power-distribution challenges encountered during the testing of these complex SoCs will be given. Increasing power density and the leakage tails incurred due to relentless process variations leads to aggravated thermals on chip. Additionally, during test modes, such issues exacerbate due to compromise between test-time, coverage; often leading to a burst of activity in very short span of time. Such thermal excursions can eat into reliability as well as voltage margins of the critical paths, eventually leading to ‘false’ failures. In this tutorial, analysis techniques involved along with custom methodologies developed for faster analysis will be presented. In addition, various knobs involved in alleviating thermal challenges ranging from die, package to system level will be covered in tutorial.
Jais Abraham
Jais Abraham is Sr. Director of Design Engineering at Qualcomm India Pvt. Ltd., where he focuses on the Design-For-Test methodology. After graduating in Electronics Engineering from IIT- Chennai, he worked at Texas Instruments, AMD and at Intel, looking into the DFT of various classes of products ranging from extremely cost-sensitive products to high-speed processors and products with stringent quality requirements. Jais has co-authored multiple technical papers in various conferences and is a co-inventor of 11 US patents.
Palkesh Jain
Palkesh Jain graduated from IIT Bombay with dual degree in Electrical Engg and holds a doctoral degree (cum laude) in CS from Universitat Politècnica de Catalunya, Barcelona. He worked with Texas Instruments India from 2004-14, where he and team delivered on Gigahertz enabling design reliability methodologies for several generations of OMAP, ASIC, DSP and automotive devices. He joined Qualcomm in 2014, where he currently serves as Senior Director, Technology. He and team have been focusing on thermal and PDN challenges for diverse Qualcomm designs. Palkesh has >25 awarded US patents and 30+ publications in IEEE Transactions/conferences.
Subhadip Kundu
Subhadip is a Sr. Staff Engineer in Qualcomm. His works mostly focuses on creating in-house, industry leading solutions for silicon debug and characterization, fault modeling, and test time optimizations. He has also prior experience as Sr R&D Engineer in Synopsys where he has developed algorithms/software used in commercial EDA based ATPG, Diagnostics. Subhadip has significant contributions in multiple conferences. He has published 30+ journal/conference papers (including multiple ITC USA, DAC, DATE, TCAD, TVLSI, ISTFA). He has received Best Paper Award in ISTFA 2021, and his Paper was nominated in DAC best research paper 2013. His PhD work received 3rd place TTTC thesis award. He Holds 2 US Patents on Diagnostics.
Nikhil Patil
Nikhil Patil is working at Qualcomm India PVT LTD as Staff Engineer. He is responsible for SoC Thermal analysis and signoff since 2017. He holds a Master of Science (By Research) degree in Electrical Engineering from Indian Institute of Technology Madras. As a SoC Thermal Engineer, Nikhil works on thermal aspects of SoC at multiple levels such as architecture, process, physical design to testing. He has specialty in methodology development and automation of workflows, which have been used over generation of Snapdragon processors and in evaluation of thermally constrained benchmark scores, as well as alleviating post-Si thermal challenges. Nikhil has authored papers in peer-reviewed journals/international conferences and many of his technology innovations have culminated in USPTO applications.
Short Tutorial 1
Title: Synchronous Interface Test Challenges for Complex ASIC, Practical Solutions for At-Speed Test
Authors: Veerabhadrarao Vasa and Vevekanenda G
Company: Google
Tutorial Abstract:
Complex digital Intellectual Properties (IPs) like GPUs and CPUs are often partitioned into multiple physical partitions for improved design convergence and overall Quality of Results (QoR). This partitioning aids in reducing design complexity, enhancing timing closure, facilitating design reuse, and shortening development cycles. These complexities are further accentuated by multiple asynchronous clock domains, heterogeneous voltage and power domains, and limitations imposed by DFT wrapper insertion tools. Physical blocks within ASIC partitions are strategically abutted for compact and routable layouts that meet stringent timing constraints. Though scan wrapper cells provide modularity in test, true at-speed structural testing often necessitates custom methodologies to balance test application time constraints and low-power test requirements. Due to inherent hierarchical design structure, varying implementation styles, and design elements falling under the purview of difficult-to-test logic, achieving lower DPPM (Defective Parts Per Million) requires meticulous planning of core wrapping strategies, ATPG partitioning, scan chain phasing, test mode selection, and custom design-for-testability (DFT) modifications to meet coverage and test application time benchmarks. This tutorial explores practical challenges faced in contemporary CPU and GPU designs, presents methods for achieving DFT goals, and demonstrates the results of these techniques.
Veerabhadra Rao
Veerabhadra Rao Vasa, DFT at Google IT Services India Pvt. Ltd
Veerabhadra Rao has worked on various DFT aspects from Scan/memory test architecture, to Silicon bring-up for multiple SoCs [Mobile Compute, Automotive & Space applications] and has delivered successful tape-outs with first pass silicon. His areas of interest are Low power DFT, Memory test, Test Quality, First Pass silicon, Automation & has filed 2 patents on at-speed test strategies. He has over 17 years of industry experience and worked at Intel, Microsemi, ISRO. Currently working at Google India Silicon team as DFT Manager & Technical lead.
Vevekanenda Gonugunta
Vevekanenda Gonugunta, DFT at Google IT Services India Pvt. Ltd. Vevekanenda Gonugunta is a DFT Engineer with Google and has over 9 years of experience in DFT and system design. Vevek’s primary areas of interests include SCAN, ATPG, Coverage, Low power DFT, post-silicon debug and methodology automation.
Short Tutorial 2
Title: Addressing Test, Safety and Security for Connected Automotive IC’s
Authors: Lee Harrison
Company: Siemens EDA
Tutorial Abstract:
The exponential growth of electronics in automobiles have stimulated significant innovation towards the development of advanced safety mechanisms. At the same time, as automotive ICs are being manufactured in smaller technology nodes, which means maintaining high quality and reliability continues to challenge the safety targets. As we rise to these new challenges for test, safety and security it has inevitably resulted in advances in the technology we deploy to detect and monitor defects as well as anomalies in both the silicon and the system. Coupled with the requirement to continue this monitoring for the life cycle time of the device rather than at just the manufacturing stage. In order to address these requirements, it is necessary let to and this has initiated an inevitable collaboration between technology provides in all of these areas to provide accomplished unparalleled safety and integrity of automotive ICs.
Lee Harrison
Lee Harrison is Director, Product Marketing, with Siemens Tessent Division. He has over 20 years of industry experience with Siemens Tessent DFT products and has been involved in the specification of new test features and methodologies for Siemens customers, delivering high quality DFT solutions. With a focus on safety and security, Lee is working to ensure that current and future DFT requirements of Siemens’s Automotive customers are understood and met. Lee Received his BEng in MicroElectronic Engineering from Brunel University London in 1996. Lee presents regularly at industry conferences such as DAC, ITC, VTS, ETS, DATE etc.
Short Tutorial 3
Title: Ensuring robust RTL for DFT: Comprehensive verification strategy
Authors: Parth Kadiya, Piyushkumar Chaniyara, Mahipal Reddy, Satish Sajjanar and Pervez Garg
Company: Texas Instruments
Tutorial Abstract:
This abstract delves into a meticulous verification strategy for establishing a robust RTL for Design for Testability (DFT). Encompassing crucial elements including Jasper Gold SuperLint checks, Connectivity checks, TCL checks, Functional checks, Scan coverage estimation and Test Mode Entry Checks at RTL level and generating & verifying ATPG collaterals at RTL level. In traditional flow; lot of the DFT issues are identified while running ATPG or Simulation during late-Compile2 or Compile3 leading to late ECOs and project delays. With the proposed methodology, a majority of them are targeted to be addressed at initial RTL development stages. The comprehensive approach aims to fortify the RTL against potential flaws, late design bugs and ensuring a robust foundation for DFT integration. The proposed strategy seeks to enhance the reliability and quality of RTL designs, contributing to the overall success of DFT implementation in TI designs.
Parth Kadiya
Parth is DFT engineer with more than 5 years of experience in the field. He has been associated with Texas Instruments since Dec 2020 and have worked across multiple teams in Processors. He enjoys working on new and challenging problems, with continuous learning rigour.
Mahipal Reddy
Mahipal joined TI India in 2023 after completing his masters from BITS Pilani. He is a Design Engineer in Sitara MPU team and has worked on DFT-LINT, IP & SoC ATPG and simulations
Satish Sajjanar
Satish is a DFT engineer with more than 6 years of experience in the field. Along with the DFT execution across various test aspects, he is also heavily involved in flow automation and key enabler for existing DFT flows developed for Processors devices.
Piyushkumar Chaniyara
Piyush is DFT engineer with more than 7 years of experience in the field. He has been associated with Texas Instruments since 2021 and has worked across multiple teams in Processors. He has expertise in both pre-silicon development and post-silicon validation.
Pervez Garg
Pervez manages TI Processors DFT team in India. His interests are defining novel DFT architecture for low power test, optimized test cost, DFT implementation for mixed signal designs, post-silicon debug and enabling ways for DFT to optimize the device architecture & implementation.
Short Tutorial 4
Title: DFT Designer’s Nightmare in the Nanometer Age
Authors: Ankush Srivastava and Kamlesh Pandey
Company: Qualcomm
Tutorial Abstract:
The tutorial aims to discuss issues related to signal integrity, power integrity, process variability, and CMOS reliability [Ankush ITC 2022, Ankush JETTA 2017, Wang 2004, Saxena 2003] which either ends in full at-speed ATPG vector regeneration or selectively performing long-hour silicon debugs. Most experts expect that Moore’s law will hold for at least one more decade. Die size will continue to grow larger, but, at the same time, minimum feature size will continue to shrink. Although smaller transistor size can result in smaller circuit delay, a smaller feature size for interconnects does not reduce the signal propagation delay; thus, the signal propagation delay in interconnects has been the dominant factor in determining the delay of a circuit [Dally 1998, Ankush ATS 2015]. Before we discuss real silicon cases, spatial and temporal reliability needs to be understood for CMOS as well as interconnects.
Ankush Srivastava
Ankush Srivastava is currently involved in enabling Industry leading design-for-test (DFT) methodologies for Qualcomm’s state-of-the-art SoCs. Prior to this, he worked at Freescale/NXP Semiconductors, India Design Center for 12 Years. Received the Ph.D. from Indian Institute of Technology Bombay, Mumbai and the M.E. from the Birla Institute of Technology and Sciences, Pilani, India, all in Electrical Engineering. He holds several international patents, journals and presented various papers in premier IEEE conferences. His current research interests include defining DFT architecture of complex SoCs, system security related to debug interfaces, effective and efficient small-delay defect-oriented test generation and low-power test.
Kamlesh Pandey
Kamlesh is currently working as a Founder and CEO at Krivya Semicon Pvt Ltd from Feb 2024. The primary goal of the Krivya Semicon is to develop test automation tools in the next 3 to 4 years. In the past Kamlesh has worked as a Director of Engineering at Qualcomm India. He led Bangalore ATPG group for 2.5 years and managed ATPG of automotive, wearable, mobile infrastructure, mobile handset, compute and XR/VR SOCs. Prior to joining Qualcomm, Kamlesh has worked at Broadcom India Pvt Ltd for 17 years and his last designation at Broadcom was Distinguished Engineer/Technical Director. At Broadcom, Kamlesh has invented in-house at-speed test architecture known as CTSA, architected and designed secure JTAG and boundary scan, In-house Logic BIST for security processor, Analog BIST for Video DAC, Loopback based DDR BIST, and JTAG based low pin count scan testing. His areas of interest are defect based testing, at-speed test architecture, scan compression, analog and mixed signal testing, ultra-low cost testing. In 23 years of career, he has contributed to the productization of 70+ SOCs. He received M.Tech. in Microelectronic and VLSI systems from Indian Institute of Technology Kanpur, India in 2001.
Short Tutorial 5
Title: Fault Modeling in Digital Integrated Circuits: How It Influences ATPG and DfT
Authors: Bhargab B. Bhattacharya and Susmita Sur-Kolay
Organization: Indian Statistical Institute, Kolkata
Tutorial Abstract:
The technology of integrated circuits (ICs) has revolutionized human society in the last six decades by redefining civilization. While the first planar microchip in the sixties had only four transistors, present-day IC’s encapsulate tens of billions of transistors on a tiny piece of silicon that empower modern computing platforms, control systems, and communication infrastructure. Building such colossal systems raises many fundamental questions: How is the design complexity managed? How is the reliability of operations ensured? Is the given system robust and dependable? How such a large multi-core system-on-chip be tested for functional correctness? What is the computational complexity of test generation? How can the physical defects on a chip that appear during its fabrication or while it is in use, be logically modeled? In this tutorial, we revisit various fault models for digital ICs that have been discovered and utilized by test engineers over several decades.
Bhargab B. Bhattacharya
Bhargab B. Bhattacharya had been on the faculty of Indian Statistical Institute, Kolkata, for more than three decades. He later joined the faculty of Computer Science & Engineering at Indian Institute of Technology Kharagpur as Distinguished Visiting Professor. He also served as Visiting Professor at the University of Nebraska-Lincoln, and Duke University, USA, at the University of Potsdam, Germany, at Tsinghua University, Beijing, China, and at NIT Rourkela. He received the B.Sc. degree in physics from the Presidency College, Kolkata, B.Tech. and M.Tech. degrees in Radiophysics and Electronics, and the PhD degree in Computer Science, all from the University of Calcutta.
Dr. Bhattacharya’s contributions encompass the domains of VLSI design and test, fault-tolerance, image analysis, and microfluidic lab-on-chips. He has published more than 400 technical articles, authored/edited five books, and he holds one Indian and ten US Patents.
Dr. Bhattacharya is the recipient of the VASVIK Industrial Research Award for Electronic Sciences and Technology (1999); India Semiconductor Association TechnoMentor Award (2008); INAE Outstanding Teachers Award (2014); IEI-IEEE Joint Award for Engineering Excellence (2018); Lifetime Achievement Award for Contributions to VLSI Testing (2019), and Shri Om Prakash Bhasin Research Award in Electronics and Information Technology (2022). He was named INAE Chair Professor (2016 – 2018), and AICTE-INAE Distinguished Visiting Professor (2018 – 2020). He is Fellow of the Indian National Academy of Engineering, Fellow of the National Academy of Sciences (India), Fellow of the Asia-Pacific Artificial Intelligence Association (AAIA), and Fellow of the IEEE.
Susmita Sur-Kolay
Susmita Sur-Kolay received the B.Tech. (Hons.) degree in Electronics and Electrical Communications Engineering from the Indian Institute of Technology Kharagpur, and the Ph.D. degree in Computer Science and Engineering from Jadavpur University, India. She has been a faculty member in the Advanced Computing and Microelectronics Unit of the Indian Statistical Institute, Kolkata since 1999, where she is presently Professor. Earlier, she served as Reader in the Department of Computer Science and Engineering at Jadavpur University, Kolkata. Prior to that, she was a post-doctoral fellow at the University of Nebraska-Lincoln, and a Research Assistant at the Laboratory for Computer Science in Massachusetts Institute of Technology. She was also on sabbatical to Princeton University and to Intel Corp., USA. Her research contributions include electronic design automation for VLSI physical design, fault modeling and testing, synthesis of quantum computers, and graph algorithms. She authored several technical papers in leading international journals and conference proceedings, and a chapter in the Handbook on Algorithms for VLSI Physical Design Automation. She served as General Co-Chair of 2016 International Conference on VLSI Design (2005); Technical Program Co-Chair of 2005 International Conference on VLSI Design, the 11th Symposium on VLSI Design and Test (2007), and ISVLSI 2011. She had been on the editorial board of the IET Computers and Digital Techniques, and IEEE Transactions on VLSI Systems. She is a Distinguished Visitor of the IEEE Computer Society (India), Senior Member of IEEE, Member of ACM, IET and VLSI Society of India. Among other awards, she was the recipient of the President of India Gold Medal (summa cum laude) at IIT Kharagpur (1980), IEEE Women in Engineering Inspiring Member of the Year (2014), Distinguished Alumnus Award of IIT Kharagpur (2020), and Women in Technology Leadership Award of the VLSI Society of India (2022). In 2023, she has been named Fellow of the Indian National Academy of Engineering (FNAE).
Short Tutorial 6
Title: Effective Low-Cost Strategies for Detecting Recycled Integrated circuits
Authors: Ujjwal Guin
Organization: Auburn University
Tutorial Abstract:
The escalating threat of counterfeit integrated circuits (ICs) and system-on-chips (SoCs) sourced from discarded electronics, repurposed, and marketed as new is a mounting concern exacerbated by the absence of robust detection methodologies. Infiltration of such fake ICs into our critical systems integral to the global infrastructure poses a grave risk, potentially precipitating system failures and security breaches with far-reaching implications for societal welfare. Recycled ICs frequently exhibit reduced reliability, shortened remaining lifetime, and compromised performance. The crude recycling process involving disassembly, cleansing, and reassembly, typical in rebranding recycled components as new, can introduce additional defects and anomalies, including electrostatic (ESD) damage and other defects, leading to operational failures. Given that many Department of Defence (DoD) systems surpass the expected lifespan of their electronic components, relying heavily on a continuous supply of legacy commercial off-the-shelf (COTS) components for maintenance and repair, encounters with recycled parts are frequent. Hence, efficient counterfeit detection methods are imperative to avert the pervasive infiltration of such components into the semiconductor supply chain.
Ujjwal Guin
Ujjwal Guin is currently an Associate Professor at the Department of Electrical and Computer Engineering at Auburn University. He received Bryghte D. and Patricia M. Godbold Associate Professorship for the highest research, teaching, and service achievements at Auburn University. He received his Ph.D. degree from the University of Connecticut in 2016. He is actively involved in Hardware Security and Trust, Supply Chain Security, Cybersecurity, and VLSI Design and Test projects. He has developed several on-chip structures and techniques to improve integrated circuits’ security, trustworthiness, and reliability. He co-authored the book ”Counterfeit Integrated Circuits: Detection and Avoidance”. He also authored two book chapters, thirty journal articles, and over forty refereed conference papers. His work has been recognized through several best paper nominations, awards, research grants, and prizes from various security competitions. One of his papers referenced in the ”White House 100-Day Reviews under EO 14017” report, specifically in the context of ”Building Resilient Supply Chains,” dated June 2021. His projects are 1 sponsored by the United States Army, Air Force Office of Scientific Research (AFOSR), National Science Foundation (NSF), and Air Force Research Laboratory (AFRL). Dr. Guin was actively involved in developing a web-based tool, Counterfeit Defect Coverage Tool (CDC Tool), http://www.sae.org/standardsdev/cdctool/. This tool has been adopted in ”AS6171: Test Methods Standard; General Requirements, Suspect/Counterfeit, Electrical, Electronic, and Electromechanical Parts” for the basis of test method selection and evaluation of test effectiveness. He currently serves or has served several technical program committees in several reputed conferences, such as DAC, HOST, VTS, PAINE, VLSID, GLSVLSI, ISVLSI, and Blockchain. He is the Vice-program Co-Chair of HOST and Student Activities Chair of VTS. He is a senior member of IEEE and a member of ACM
Conference Location
Radisson Blu Hotel, Bengaluru , India. (Marathahalli, Outer Ring Road)
Address: 90/4 Outer Ring Road, Marathahalli, Bengaluru, 560037, India
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To Be Decided (TBD)