Menu
Keynote Sessions
Keynote 1
Title: “Evolution of Semiconductor Test – Going beyond traditional production screening“
Sundarrajan Subramanian – VP Engineering, Design Management, Qualcomm, India
Bio:
Sundarrajan Subramanian is VP Engineering at Qualcomm Bangalore and is responsible for managing the SoC Front-End organization for India HW. The SoC Front-End functions include Design, Design Verification (DV), Design-For-Test (DFT) and Security, Power management, Debug cores development. The SoC Front-End teams in India (Bangalore, Noida and Hyderabad) are responsible to deliver end-to-end products spanning multiple technology nodes and varied markets across Mobile, IoT, Automotive, XR, and so on. Sundar’s previous responsibilities at Qualcomm include leading the SoC development and productization for Qualcomm thin modems across multiple generations. He has prior experience with Teradyne (USA), Cisco Systems (USA), Texas Instruments ( India) in the areas of Design-For-Test (DFT), Implementation, Post-Silicon debug, and Design Management. Sundar is associated with Qualcomm for 10+ years and in the VLSI industry for more than 25 years and hold a Master degree in Solid State Electronics from Arizona State University, USA.
Abstract:
“Semiconductor Test” has been associated with screening defective devices before shipment to customers for a long time. Growing SoC complexities, tighter time to market, stricter Quality & Reliability requirements and an optimized Test-Cost Environment have long driven innovation for the test community. As companies continue to invest in DFT and Non-DFT (Functional/System) test infrastructure with a primary goal of Production Screening, it has become insightful to leverage this investment and go beyond traditional production screening. The objective is to “Learn and Improve” in addition to the traditional screening. Diverse market segments like AI, Mobile, Automotive, Server, Laptops, IoT have their unique product KPIs to win their competitive marketplace. The product KPIs for such diverse SoC market segments are influenced by design architecture, VLSI flows and methodologies, packaging, S/W & system, and SoC’s silicon performance. Large scale data analytics with customized learning models are on the forefront of driving this learning. Today’s “Semiconductor Test” will drive tomorrow’s improved product KPIs and market competitiveness. This talk will share interesting insights into how Qualcomm sees “Semiconductor Test” evolve in the days ahead – where Semiconductor Test goes beyond traditional production screening.
Keynote 2
Title: “Fault-Criticality Classification and Test Solutions for Systolic Array-Based AI Hardware“
Krishnendu Chakrabarty, Arizona State University
Bio:
Krishnendu Chakrabarty received the B. Tech. degree from the Indian Institute of Technology, Kharagpur, in 1990, and the M.S.E. and Ph.D. degrees from the University of Michigan, Ann Arbor, in 1992 and 1995, respectively. He is now the Fulton Professor of Microelectronics in the School of Electrical, Computer and Energy Engineering at Arizona State University (ASU) and Chief Technology Officer (CTO) of the Department of Defense Microelectronics Commons Southwest Advanced Prototyping (SWAP) Hub. He is also the Director of the ASU Center on Semiconductor Microelectronics. Before joining ASU, he was the John Cocke Distinguished Professor and Department Chair of Electrical and Computer Engineering (ECE), and Professor of Computer Science, at Duke University.
Prof. Chakrabarty is a recipient of the National Science Foundation CAREER award, the Office of Naval Research Young Investigator award, the Humboldt Research Award from the Alexander von Humboldt Foundation, Germany, the IEEE Transactions on CAD Donald O. Pederson Best Paper Award (2015), the IEEE Transactions on VLSI Systems Prize Paper Award (2021), the ACM Transactions on Design Automation of Electronic Systems Best Paper Award (2017), and over a dozen best paper awards at major conferences. He is also a recipient of the IEEE Computer Society Technical Achievement Award (2015), the IEEE Circuits and Systems Society Charles A. Desoer Technical Achievement Award (2017), the IEEE Circuits and Systems Society Vitold Belevitch Award (2021), the Semiconductor Research Corporation Technical Excellence Award (2018), the Semiconductor Research Corporation Aristotle Award (2022), the IEEE-HKN Asad M. Madni Outstanding Technical Achievement and Excellence Award (2021), and the IEEE Test Technology Technical Council Bob Madge Innovation Award (2018). He is a Research Ambassador of University of Bremen (Germany) and he was a Hans Fischer Senior Fellow at the Institute for Advanced Study, Technical University of Munich, Germany during 2016-2019. He is a 2018 recipient of the Japan Society for the Promotion of Science (JSPS) Invitational Fellowship in the “Short Term S: Nobel Prize Level” category. He is a recipient of the Distinguished Alumnus Award from the Indian Institute of Technology, Kharagpur.
Prof. Chakrabarty’s current research projects include: design-for-testability of 2.5D/3D integrated circuits and heterogeneous integration; AI accelerators; microfluidic biochips; hardware security; AI for healthcare. He has supervised 40 PhD dissertations and mentored 12 postdoc researchers.
Prof. Chakrabarty is a Fellow of ACM, IEEE, and AAAS, and a Golden Core Member of the IEEE Computer Society. He was a member of the DARPA Microsystems Exploratory Council during 2022-2023. He is a member of the Scientific Advisory Board of the Deutsches Forschungszentrum für Künstliche Intelligenz (German Research Center for Artificial Intelligence). He was a Distinguished Visitor of the IEEE Computer Society (2005-2007, 2010-2012), a Distinguished Lecturer of the IEEE Circuits and Systems Society (2006-2007, 2012-2013), and an ACM Distinguished Speaker (2008-2016). Prof. Chakrabarty served as the Editor-in-Chief of IEEE Design & Test of Computers during 2010-2012, ACM Journal on Emerging Technologies in Computing Systems during 2010-2015, and IEEE Transactions on VLSI Systems during 2015-2018.
Abstract:
The ubiquitous application of deep neural networks (DNN) has led to a surge in demand for AI accelerators. Fault-criticality analysis identifies faults that cause significant deviations from acceptable requirements such as inferencing accuracy. This talk will focus on how AI can be used for classifying the criticality of structural faults in the processing elements (PEs) of systolic-array accelerators. The speaker will first present a two-tier machine learning-based method to assess the functional criticality of faults. While supervised learning techniques can be used to accurately estimate fault criticality, it requires a considerable amount of ground truth for model training. To address this problem, the speaker will present a neural-twin framework for analyzing fault criticality with a negligible amount of ground-truth data. Next, the speaker will describe a black-box optimization method to generate functional test patterns for AI accelerators and ensure transferability between PEs in the systolic array. Lastly, a fault localization solution based on checksums will be presented to enable low-cost runtime error recovery.
Keynote 3
Title: “Accelerated Compute’s Impact on Test Development“
Bill Cornwell - AVP, CCS (Custom, Compute & Storage) DFT, Marvell
Bio:
Bill Cornwell is AVP of Hardware Engineering at Marvell and leads the Custom, Compute & Storage Design for Test (CCS-DFT) organization. The CCS-DFT team is global team responsible for test solutions in advanced process notes for high core-count AI compute platforms, 5G and 6G acceleration, and custom ASIC designs. The reticle size silicon challenges the design and manufacturing limits and leading technologies including multi-chip modules leveraging both 2.5D and 3D solutions. Bill has extensive experience in the semiconductor industry, having previously led Marvell’s ASIC and Physical design teams. In this role, the developed test solutions (architecture to mass production) and completed physical implementation including releasing to manufacturing of designs in 5nm, 7nm and 14nm technology nodes. After receiving his Masters in Electrical Engineering from NC State University, Bill started his career with IBM Microelectronics as an analog designer and held leadership multiple roles. Bill led the team through the IBM to GlobalFoundries and GlobalFoundries to Marvell acquisitions.
Abstract:
As the demand for accelerated computing continues to grow, so does the complexity of chip designs and the criticality of test. With a semiconductor Total Addressable Market (TAM) exceeding $80 billion USD in 2023 and still growing, accelerated computing will play a crucial role in shaping our future test solutions. The presentation covers the importance of new and innovative test solutions required to support accelerated compute in both pre-silicon (design and implementation) and post-silicon (fabrication through Mass Production Ready). In pre-silicon, we need solutions that can handle the scale of accelerated compute chip designs. This includes incorporating new tool features from Electronic Design Automation (EDA) vendors, rethinking how we partition the design for testing, and addressing the need for multi-chip modules (both 2.5D and 3D). These challenges drive the need for continued innovation and the establishment of new standards such as IEEE 1838. In post-silicon, the increasing complexity of our package solutions compels us to rethink what is achievable during manufacturing testing. For example, simpler solutions make long wafer test times cost-prohibitive, complex (expensive) modules are now reversing that trend and driving more towards wafer testing. Additionally, the longer module assembly time results in more sophisticated wafer testing, drives the need for accelerated hardware learning and reducing time to market.
Keynote 4
Title: “In the Decade of AI, Expectations from the DFT Community: An Outsider’s Perspective“
Subash Chandar Govindarajan, Senior Director, Google Silicon, India.
Bio:
Subash Chandar Govindarajan is the Silicon site lead for Google Bangalore. He has over 27 years of experience in the semiconductor industry and has held several leadership positions. Subash holds a master of science in engineering degree from Indian Institute of science, Bangalore. He holds 9 US patents and has over a dozen publications in international conferences. He is passionate about building vibrant organizations and nurturing technological innovations.
Abstract:
The 2020s have ushered in an era of unprecedented AI and ML acceleration, driven by heterogeneous chips boasting billions of transistors. This exponential growth in complexity places immense pressure on Design for Test (DFT) to ensure not just functional correctness, but also yield improvement, efficient debug and security.
The following challenges in the DFT community creates a need to re-evaluate traditional approaches in the face of emerging demands:
- The Insufficiency of Structural Patterns: We question the adequacy of traditional structural test patterns for characterizing increasingly complex parametric variations in modern SoCs.
- DFT’s Role in Functional Debug: Can DFT truly streamline functional debug, or is it falling short in the face of complex software-hardware interactions?
- Security Concerns in DFT: How can DFT evolve to address the growing threats of hardware Trojans and other security vulnerabilities?
- True Power Testing: With power consumption a critical concern, are current DFT methodologies equipped to accurately assess and optimize power usage
- Cost-Effectiveness: As DFT overhead rises, how can we balance the need for thorough testing with the economic pressures of minimizing chip area and test costs?
- System-Level Test: Are traditional chip-level tests sufficient in the age of complex system-on-chip (SoC) applications, or do we need a paradigm shift towards system-level testing?
- Yield Improvement through AI/ML: Can AI and ML techniques revolutionize yield analysis and optimization, going beyond traditional DFT methods?
- Low-Footprint DFT: Is it possible to maintain DFT area overhead below 5% in the face of growing chip complexity?
Key takeaways:
- A fresh perspective on the limitations and opportunities in current DFT practices.
- A call to action for the DFT community to innovate and adapt.
- Insight into the specific areas where DFT needs to evolve to meet the demands of the AI decade.
Keynote 5
Title: “From chip to system – The expanding world of test“
Lee Harrison, Director of Product Marketing, Siemens EDA
Bio:
Lee Harrison is Director, Product Marketing, with Siemens Tessent Division. He has over 25 years of industry experience with Siemens Tessent DFT products and is involved in the specification of new test features and methodologies for Siemens customers, delivering high quality DFT solutions. With a focus on safety and security, Lee is working to ensure that current and future DFT requirements of Siemens’s customers are understood and met. Lee received his BEng in MicroElectronic Engineering from Brunel University London in 1996. Lee presents regularly at industry conferences such as DAC, ITC, VTS, ETS, DATE etc.
Abstract:
As we continue to see semiconductor technology evolve. From the introduction of smaller and smaller process nodes, the increased complexity of designs moving from flat to hierarchical to multi-die devices. The requirements from system integrators are also evolving and it is no longer just enough to have high quality manufacturing test. From safety requirements for automotive applications, to the challenge of silent data errors in data centres. There is an increasing need for extensive in-system testing and on-chip monitoring. All generating a wealth of different but valuable data. The way in which this data is used will drive the quality of not just our semiconductors but complete systems.
Conference Location
Radisson Blu Hotel, Bengaluru , India. (Marathahalli, Outer Ring Road)
Address: 90/4 Outer Ring Road, Marathahalli, Bengaluru, 560037, India
Google Maps:
Click here for Direction
To Be Decided (TBD)