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Industry Sessions
Title: “Test Challenges in the AI & Chiplet era“
BIO OF PRESENTER:
Rajesh Vaddempudi is currently the Senior Vice President of Engineering at Tessolve and heads the Test Engineering Division.
Over 24 years of experience with a solid track record of driving revenue growth, leading organizations, and enhancing strategic partnerships. As the P&L owner for global Test Engineering services, specialize in a range of technologies, including Digital, Analog, Mobile, Automotive, Cloud, and AI. These efforts have successfully expanded the Tessolve Test Business Unit to include over 1000+ engineers across divisions such as Bench Characterization Engineering, Test and Product Engineering, Quality, and Automation. Most recently, have set up Test labs with high-volume manufacturing equipment in San Jose and Austin, which are equipped with advanced Automated Test Equipment (ATEs), Probers, and Handlers, setting new standards in industry capabilities.
ABSTRACT:
This presentation will highlight challenges and current thought process for all facts such as DFT, bring up, char, Qual and release to high volume manufacturing of High performance, Hyper scalar AI enhanced chips.
Title: “Navigating the Complexities of Test Engineering“
BIO OF PRESENTER:
Mudasir Kawoosa is a DFT Architect at Texas Instrument India and has been with the industry from past 13 years.
In addition, he is a Senior Member of Technical Staff and manages the centralized DFT team in the Connectivity Business Unit. He holds Masters in Electrical Engineering from Indian Institute of Technology, Madras, has authored 30+ internal and external publications and continue pioneering innovative test solutions as reflected through 10 granted US patents. His area of interest spans from basic to advanced DFT techniques, low power test, low pin test solutions besides successful first pass silicon bring up and hard to resolve silicon issues.
ABSTRACT:
In the rapidly evolving landscape of semiconductor manufacturing, test engineering has always been a critical domain that ensures product quality, reliability and compliance with the specifications.
While the aim is to enhance the testability of device, this domain faces numerous challenges.
In this presentation, we will review few of these challenges listed below and provide insights into commonly used practices in the industry to address them.
1. Strategic test planning: Comprehensive overview across diverse TI SoCs and their test dynamics.
2. Unified DFT framework: Architecture, implementation and reusability.
3. Conquering test entitlement: Maximising test coverage, balancing test area overhead and combatting test power dissipation.
4. Test cost reduction: Techniques for improving test concurrency and facilitating higher multi- site testing.
As these challenges profoundly influences the test engineering, their meticulous analysis combined with innovative solutions helps to align in delivering high quality and reliable SoCs.
Title: “Expedite time to market by optimizing the test program development cycle time using AI/ML algorithms utilizing synthetic data generation“
BIO OF PRESENTER:
Kalyana Sundaram Chandran possessing 18 years of experience and he is currently working as a Scrum Lead at Caliber Interconnect Solutions, where he focuses on testing digital and mixed-signal ICs using various tester platforms. He specializes in research and development, creating advanced testing techniques and methodologies to drive product innovation and quality. His notable contributions in R&D also include progress in biomedical VLSI signal processing and programming in Verilog and VHDL. He has an impressive academic record with 25 international journal publications and over 20 papers presented at international conferences. He holds two patents and two copyrights. He earned his Ph.D. in Biomedical VLSI Signal Processing from Anna University, Chennai. Outside of work, he enjoys reading historical novels and traveling, which fuel his passion for creative thinking.
ABSTRACT:
The relentless push for miniaturization (reaching the nanometer scale) in the semiconductor industry unlocks incredible capabilities in Integrated Circuits. However, this progress comes with a hidden cost: ballooning test development costs and longer production times. This research proposes a solution to tackle this challenge: an AI-powered approach to optimize test program development.
Our solution focuses on creating efficient and high-quality test programs for wafer sorting and packaged device screening, all while streamlining the New Product Introduction (NPI) process. This is achieved by leveraging a supervised Machine Learning (ML) model built on a Multi-label associative classification approach. This model, trained on data points from design specifications and corresponding test plans, acts as an intelligent assistant, generating seamless test programs for any given ASIC. The result is a significant boost in test efficiency compared to conventional methods, leading to a dramatic acceleration in time-to-market.
Looking beyond this specific solution, this research also paves the way for the future of the industry by showcasing the potential of advanced AI-powered testing strategies across any advanced complex designs including Automotive/IOT/AI/Bio-Chips with the support from the integration of synthetic data generation.
Title: “The fallacy of Low Toggle at-speed ATPG vectors in FTRV Mission“
BIO OF PRESENTER:
Ankush Srivastava is currently involved in enabling Industry leading design-for-test (DFT) methodologies for Qualcomm’s state-of-the-art SoCs. Prior to this, he worked at Freescale/NXP Semiconductors, India Design Center for 12 Years. Received the Ph.D. from Indian Institute of Technology Bombay, Mumbai and the M.E. from the Birla Institute of Technology and Sciences, Pilani, India, all in Electrical Engineering. He holds several international patents, journals and presented various papers in premier IEEE conferences. His current research interests include defining DFT architecture of complex SoCs, system security related to debug interfaces, effective and efficient small-delay defect-oriented test generation and low-power test.
ABSTRACT:
The talk aims at understanding the issues of over-testing due to power supply droop during at-speed scan testing. It will start with the problem definitions and most recent solutions being offered either from the hardware designers or using CAD centric solutions. It will be proceeded by the pre-silicon and post-silicon hot-spot analysis with their respective effectiveness. At the end, we suggest effective strategies to minimize parametric yield loss due to over testing and possible efficient solutions available today.
Index Terms— Automated Test Pattern Generation (ATPG), At-speed Test, Low Power Test, Shift/Capture Power, Local Hot-Spot, Power-aware Test, Voltage Droop
Target Audience— Any students or professionals who have worked with ATPG in the past with additional awareness in compression/decompression techniques while generating ATPG vectors.
Title: “Targeting bridges and opens with physical defect-based approach“
BIO OF PRESENTER:
Suraj MC is Principal Engineer in the Central CAD and Design Services (CCDS) team which is part of Central Engineering at Marvell. He has around 14 Years of extensive experience in DFT from architecture to silicon bring-up. He earned his graduation in electronics and comm from Govt Engg college Kannur in 2008.
BIOS OF Co-AUTHORS:
Vivek Nagarajan is Staff DFT Engineer, at Marvell. He has around 7 years of experience in DFT. He earned his Masters in VLSI Design from Anna University Chennai in 2017.
Sriram Prasath is Staff DFT Engineer, at Marvell. He has around 5 years of experience in DFT. He earned his Graduation in ECE from KPRIET Coimbatore in 2019.
ABSTRACT:
This Session talks about about physical defect oriented ATPG pattern generation methodology used to target bridge and open faults. The talk also compares the traditional method with the novel critical area-based approach and discusses the implementation results from a chip on latest node. The methodology uses siemens Tessent scan diagnosis tool where the defect is modelled using layout aware User Defined Fault models (UDFM). The UDFM for bridge or open uses physical data from layout and defects are prioritized based on their probability on silicon. One defect can have more likelihood to occur than another based on the geometry of the site. In case of a bridge, the probability on a silicon from a particular process node depend on the metal layers used, physical location, size, shape, or distance between the interconnects. This is modelled using the concept of Critical area of a fault site. A high bridge probability is reached, when the distance between the adjacent objects is minimal and the length of the bridging area is maximum and vice versa. This same critical area concept is applicable, in case of open faults. The talk provides a more efficient pattern generation methodology to target bridge or opens on DPPM critical products such as automotive.
Title: “DFT and Silicon Health Optimization with AI driven test and Silicon Life Cycle Management“
BIO OF PRESENTER:
Mohammed is the currently the Director of Solutions for clients in India. He brings with him more than 24 years of semiconductor industry experience. Mohammed began his career at Controlnet, where he helped customers deploying the Logicvision MBIST solution. He then spent more than 12 years working with prestigious clients, including TI, ST, and LSI, delivering Synopsys DFT tools. He was instrumental in establishing a DFT team, defining flows and methodologies at Western Digital for designs that were pin-limited and power-hungry.
ABSTRACT:
With the increasing need for test data volume and test time reduction, optimizing the test space has become the need of the hour. This talk throws light on such optimization capabilities and AI driven techniques. Improving silicon health and operational metrics throughout the life of a device is now becoming a reality thanks to Silicon Lifecycle Management (SLM). Built on a foundation of in-chip monitoring, data analytics and design automation, SLM is quickly becoming a cornerstone of today’s advanced SoC systems. Once deployed in-field it is essential that a device is continually monitored, tested, analyzed to allow for tuning and optimization.
Title: “Advances in a Shift-left strategy for DFT“
BIO OF PRESENTER:
Nilanjan Mukherjee is a Senior Director of Engineering for Tessent Silicon Lifecyle Solutions at Siemens EDA. He has been actively involved in the R&D of key technologies in the areas of test quality, test compression, Logic BIST, Memory BIST, low power DFT, and diagnosis. Specifically, he was involved in the development and productization of EDT/TestKompress, the VersaPoint Test Points technology, a Low Power Hybrid EDT/Logic BIST scheme for automotive ICs, and Observation Scan Technology for Logic BIST. More recently his focus is on developing new in system/in-field test solutions based on deterministic patterns (In-system TestKompress) including silicon lifecycle management for automotive and data-center markets.
Nilanjan has co-authored more than 90 technical papers and is a co-inventor of 58 US patents and several international patents. He has received numerous awards including Best Paper Awards at VTS 2020, VLSI Design 2009, ATS 2001, and VTS 1995, the Most Significant Paper Award at ITC 2012, Siemens DISW Invention of the year 2019, and the Donald O. Pederson Outstanding Paper Award in 2006.
Nilanjan received a B.Tech. (Hons) degree from IIT, India, and a Ph.D. degree from McGill University, Canada. He has given numerous tutorials, short-term courses, and invited talks at premier IEEE/ACM conferences, symposia, universities, and companies across the world.
ABSTRACT:
With an increase in the need for a more integrated silicon life cycle solution. The “shift-left” strategy is key to having these test structures integrated as part of the early design phase. Shift-Left capabilities also help enhance the ability of third-party tools to optimize area and timing when adding DFT logic prior to synthesis, leaving only scan insertion for the gate level. Design insertion happens at the RTL development stage, with RTL output, allowing seamless integration with third-party synthesis and verification software. In addition, RTL Pro generates design files that work with any downstream synthesis or verification flows, without requiring a closed-flow process.
Title: “Advancing Trustworthy Automotive Semiconductor Designs: Leveraging Modus and Midas “
BIO OF PRESENTER:
Pradeep Nagaraj is the Group Director of Product Engineering for Modus Test Solution at Cadence Design Systems in San Jose, CA.
He has been in DFT field for 24+ years in various roles in EDA, Design Implementation, and Methodology development. Prior to re-joining Cadence, he spent many years as a DFT Architect at Barefoot Networks, a startup focused on designing large programmable switches, which was acquired by Intel, and was most recently managing the DFT CAD group at Apple.
ABSTRACT:
The presentation outlines the challenges associated with the increasing complexity of semiconductor designs in the automotive industry and emphasizes how implementing effective DFT strategies are crucial to achieving highly reliable systems.
Modus Test Solution play a critical role in ensuring the safety and reliability of designs used in Advanced Driver Assistance Systems (ADAS), Highly Automated Driving (HAD), and other mission critical functionalities. As the automotive industry transitions towards zonal architectures and Battery Electric Vehicles (BEVs), the demand for high-performance semiconductors necessitates robust and efficient testing strategies and achieving comprehensive fault coverage. As part of Cadence’s Midas Safety Platform, Modus contributes to achieving the stringent functional safety requirements for these applications.
Conference Location
Radisson Blu Hotel, Bengaluru , India. (Marathahalli, Outer Ring Road)
Address: 90/4 Outer Ring Road, Marathahalli, Bengaluru, 560037, India
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