Panel Discussion

Title:Voltage bump decisions to work around Vmin issues for structural tests: are these based on any science or pure tribal art?

Abstract: Modern day SOCs are aggressively designed to consume the lowest possible power to achieve desired performance. The SOCs operate in multiple operating modes defined by voltage and frequency combinations. To guarantee robust operation, the SOCs are tested in each operating mode by applying structural and functional tests. The structural tests, comprising of memory BIST and variety of ATPG patterns, often encounter minimum operating voltage (Vmin) margin problems during phasing/volume testing. To recover yield, problematic patterns are replaced with low switching versions. Generally low toggle patterns generation step is iterated several times before the stable pattern set can be found. Beyond low toggle patterns and occasionally masking some scan cells based on failure diagnosis, some voltage bump is applied to make certain structural tests robust and eliminate yield loss. In this panel discussion, we will focus on various criteria applied in industry to determine acceptable voltage bump to address Vmin issues during post silicon debug phase. The panel will ponder upon the following questions/topics.

  1. What are possible physical defect mechanisms that can cause Vmin marginality issues?
  2. What are the reasons behind Vmin issues seen predominantly in structural tests whereas functional tests rarely require voltage bump?
  3. How to find out if further reduction of switching activities will not improve Vmin margin?
  4. What are the possibilities and nature of some real defects escaping due to voltage bump application?
  5. Will voltage bump result into any reliability issues in future?
  6. Is it possible to predict Vmin marginality and take preventive actions during PDN design?
  7. Can Vmin issues be eliminated by carefully adding some additional margins in STA signoff recipe?
  8. Why does each design module have different Vmin margin despite using same timing closure and physical implementation recipes across entire SOC?
  9. Are there any significant differences between logic Vmin and memory Vmin marginalities?


  1. Jais Abraham (Qualcomm)
  2. Srinivas Vooka (Google)
  3. Prasad Mantri (AISemiCon)
  4. Steve Palosh (Cadence)
  5. Malav Shah (Texas Instruments)

: Kamlesh Pandey (Qualcomm)