Title: “Voltage bump decisions to work around Vmin issues for structural tests: are these based on any science or pure tribal art?“
Abstract: Modern day SOCs are aggressively designed to consume the lowest possible power to achieve desired performance. The SOCs operate in multiple operating modes defined by voltage and frequency combinations. To guarantee robust operation, the SOCs are tested in each operating mode by applying structural and functional tests. The structural tests, comprising of memory BIST and variety of ATPG patterns, often encounter minimum operating voltage (Vmin) margin problems during phasing/volume testing. To recover yield, problematic patterns are replaced with low switching versions. Generally low toggle patterns generation step is iterated several times before the stable pattern set can be found. Beyond low toggle patterns and occasionally masking some scan cells based on failure diagnosis, some voltage bump is applied to make certain structural tests robust and eliminate yield loss. In this panel discussion, we will focus on various criteria applied in industry to determine acceptable voltage bump to address Vmin issues during post silicon debug phase. The panel will ponder upon the following questions/topics.
Moderator : Kamlesh Pandey (Qualcomm)