Tutorial Program

Sunday, July 23, 2023
8:00am-9:30am REGISTRATIONS
TRACKS TRACK 1
Session Chair | Santosh Kumar 		TRACK 2
Session Chair | Dr. Subhadip Kundu, Krishnamachary Prathapuram 		TRACK 3
Session Chair | Prof. R. Jayagowri
HALL NAME GRAND VICTORIA - A GRAND VICTORIA - B ARABICA & ROBUSTA
9:30 am - 11:00 am
(15 mins. Break)
11:15 am - 12:45 pm
 		Seamless Integration of packetized scan with Advanced ATE equipment
Lee Harrison (Siemens), Peter Orlando (Siemens), Michael Braun (Advantest) and Pudhukkarai Krishnan (Advantest) 		Design for Test – An indispensable slice of SOC (System on Chip) life cycle
Shamitha Rao, Bala Krishna K (Intel) 		DFX beyond Compression
Vijay Kumar K S, Kranthi Kandula, Leela Krishna Thota and Paras Chhabra (Synopsys)
12:45pm-1:45pm LUNCH BREAK
1:45 pm - 3:15 pm
(15 mins. Break)
3:30 pm - 5:00 pm
 		Error Resilient AI System: Addressing Soft Errors, Security, Threats and Manufacturing Variability Effects
Prof. Abhijit Chatterjee (Georgia Tech, USA)

Guaranteeing quality in automotive EMC tests through in-house EMC test
George Thottan, Rajesh Chauhan and Dilip Jain (Texas Instruments) 		Power Domains and Physical Synthesis – A DFT Perspective
Sarthak Singhal, Subhasish Mukherjee, Dr. Krishna Chakravadhanula and Bharath Nandakumar (Cadence)

Hierarchical and tile based DFT techniques for AI and Large SoCs
Lee Harrison and Peter Orlando (Siemens) 		Hardware Security: A perspective towards Fault Analysis Vulnerabilities
Prof. Bodhisatwa Mazumdar (IIT Indore)

Power Aware DFT
Karthik Natarajan, Likith Manchukonda, Manish Arora, Rahul Singhal and Greeshma Jayakumar (Synopsys)

Tutorial 1

Title: “The Seamless Integration of Packetized scan with Advanced ATE Equipment“

Speakers:

  • Lee Harrison, Siemens EDA
  • Peter Orlando, Siemens EDA
  • Michael Braun, Advantest
  • Pudhukkarai Krishnan, Advantest

Biographies of the presenters:

Lee Harrison, Siemens EDA

Lee Harrison is Product Marketing Director, with the Tessent product division at Siemens EDA. He has over 20 years of industry experience with Mentor DFT products and has been involved in the specification of new test features and methodologies for Mentor customers, delivering high quality DFT solutions. With a focus on Automotive, Lee is working to ensure that current and future DFT requirements of Mentor’s Automotive customers are understood and met. Lee Received his BEng in MicroElectronic Engineering from Brunel University London in 1996. Lee presents regularly at industry conferences such as DAC, ITC, VTS, ETS, DATE etc.

Peter Orlando, Siemens EDA

Peter is the SSN Product manager and part of the Siemens Tessent DFT Product Marketing team. Since joining Siemens 2018, Peter has been part of the development of SSN product and primarily responsible of the deployment of SSN. As the customer facing technical lead for the SSN product, Pete has been providing implementation guidance to external customers and internal colleagues. He’s been part of many designs that have successfully taped out with SSN. Pete’s role in SSN continues to expand with the development and deployment of new features being added to regularly.

Prior to joining Siemens, Pete has worked in the silicon industry for 29 years, with most of that time in the field of DFT, for such companies as Marvell Semiconductor, Micron Technology, ST Microelectronics, and LSI logic.

Michael Braun, Advantest

Michael Braun is a Product Marketing Manager for Semi-Conductor test at Advantest

Pudhukkarai Krishnan, Advantest

Krishnan is a Solution Architect with Advantest R&D focusing on the 93000 Tester platform. He has been in the Semiconductor Test field for more than 25 years working in various roles like applications engineering, product definition and validation, focusing on digit al and high-speed memory test areas.

Tutorial Summary: (Abstract)

This tutorial, will cover the basics of packetized ATPG data, including the hardware generation, configuration, pattern generation and ATE program creation. Detailing how this is seamlessly integrated with ATE equipment to support functions such as data logging and diagnostics.

Tutorial 2

Title: “Offset in Low Voltage Sense Amplifier and its implication on Memory Test“

Speakers:

  • Manoj Sachdeva, University of Waterloo, USA

Biographies of the presenters:

Manoj Sachdeva, University of Waterloo, USA

Manoj Sachdev‘s career as an educator, researcher, inventor and practitioner spans more than three decades. The author/co-author of 7 books and book chapters, more than 35 patents, and over 250 journal and conference publications, his pioneering concepts and developments on scaled integrated circuits have had an impact on the state-of-practice and knowledge. With a unique combination of industrial Research and Development experience and research leadership in academia, Dr. Sachdev has proposed novel, patented techniques for radiation hardened circuits, low-voltage, low-energy digital and memory circuits which attest to his stature. He, his students, and his colleagues have received several international research awards. In 1997, at the IEEE European Design and Test Conference, he received the best paper award. In 1998, he was a co-recipient of the honorable mentioned award in the IEEE International Test Conference. He received the best panel award in 2004 IEEE VLSI Test Symposium. In 2011, he was a co-recipient of the best paper award in IEEE International Symposium on Quality Electronics Design. In 2015, he was a co-recipient of the best poster award in IEEE Custom Integrated Circuits Conference. Professor Sachdev is an IEEE Fellow, Fellow of Engineering Institute of Canada, Fellow of Canadian Academy of Engineering, and has served on several conference/journal editorial committees.

Tutorial Summary: (Abstract)

Static Random Access Memories (SRAMs) often occupy a significant area of contemporary Systems on Chip (SoC) integrated circuits (ICs) and therefore determine their energy consumption, yield, and reliability. The sense amplifier (SA) is a critical SRAM circuit that requires careful design. The offset in the SA does not scale well with technology scaling and has become an impediment to realizing energy efficient SRAMs. Additionally, the offset in SAs can also give rise to intermittent failures (soft-failures) in SRAMs that are difficult to detect through traditional march test algorithms. This tutorial is divided into two parts. The first part focuses on SA design and contrasts techniques for mitigating SA offset voltage. The second part addresses test considerations for SA offset voltage. Traditional approaches of SRAM testing are inadequate to cover SA offset related failures, and we highlight algorithmic and Design for Testability (DfT) techniques for detecting such failures.

Tutorial 2

Title: “DFX BEYOND COMPRESSION“

Speakers:

  • Vijay Kumar K S, Synopsys
  • Kranthi Kandula, Synopsys
  • Leela Krishna Thota, Synopsys

Biographies of the presenters:

Vijay Kumar K S, Synopsys

Vijay Kumar K S is a Staff Solutions Engineer at Synopsys. He began his career at Texas Instruments and worked for SiCon Design Technologies and Nvidia before joining Synopsys. He has around 14 years of experience in VLSI industry working on Design for Testability (DFT). He has worked extensively on DFT implementation on multiple SoCs. Vijay’s current focus is development and deployment of Automotive DFT solutions. He leads a team of engineers working on cutting-edge DFx solutions. Vijay has a Bachelor’s degree in Electronics and Communication from R.V. College of Engineering, Bangalore.

Leela Krishna Thota, Synopsys

Leela Krishna Thota Currently working in Synopsys as Senior Solutions Engineer II, Silicon Realisation group, Hardware Analytics Team. Current work focus is on Silicon LifeCycle Management & Streaming Fabric.Overall VLSI experience is 9+ years in a collateral production role at various companies that includes the exciting work involved with Samsung Semiconductor India Research & Development(Foundry design services), Altran & SiCon Design Technologies Pvt. Ltd. Besides DFT, gained VLSI board design knowledge in Wipro. Received various accolades for the exceptional work at different clients like Microsemi (now Microchip) & Qualcomm, DRDO. Post graduated on VLSI Design from SRM University & was awarded a gold medal.

Kranthi Kandula, Synopsys

Kranthi Kandula is a RnD Manager in Hardware Design Group in Synopsys. Currently Managing Digital Design and DFT team in Synopsys for SLM (Silicon Lifecycle Management), Test and Debug IP’s. Prior to joining Synopsys she has worked at AMD in SOC DFx Validation.She has around 8 yrs of experience in VLSI industry and has worked extensively in designing, development, and validation of new DFx solutions. Current focus is involved in developing new forward-looking solutions in Silicon Lifecycle Management such as PVT Sensors, Path Margin Monitors, Insystem Test, High speed access and Automotive solutions. Kranthi has done Master’s degree in VLSI Design Tools and Technology from IIT Delhi.

Paras Chhabra, Synopsys

Paras Chhabra is a Senior Manager in Hardware Analytics and Test group of Synopsys, responsible for Hierarchical Test and Pattern Management. He joined Synopsys in 2019 from Nvidia Graphics. He has also worked with Cadence Design Systems and Mentor Graphics. Paras has a B.Tech.(H) in Electronics and Electrical Communication engineering from IIT Kharagpur, batch of 2001. He also has an M.Tech. in VLSI Design Tools and Technology from IIT Delhi.

Tutorial Summary: (Abstract)

As the advancements on the technology is mounting, the evolution of application space led the requirements of increased performance, cost reduction, faster time to market, reliability, and functionality of the chips, making designs enormous & complex. Due to the rapid growth in semiconductor market, methodologies like multi-core design, chiplets, system-on-chip (SoC) design are proposed to squeeze out every bit of performance and meet aggressive time to market goals.

Tutorial 3

Title: “Design for Test – An indispensable slice of SOC (System on Chip) life cycle“

Speakers:

  • Shamitha Rao, Intel
  • Bala Krishna K, Intel

Biographies of the presenters:

Bala Krishna K, Intel

Bala Krishna K : Bala is currently working as a Technical Lead Engineer at Intel India Pvt Ltd. He completed his Bachelors in Electronics at NIT, Warangal and Masters in Microelectronics at Manipal University. He has around 18 years of VLSI industry experience with an expertise on Design-For-Test domain for complex sub-systems and System-On-Chips across process nodes. He was involved in end-to-end industry standard DFT activities that include Architecture, Implementation, support to the Silicon screening on Automated Test Equipment and debugging of post silicon customer returns. Prior to Intel he has contributed to ASIC development in other companies like Texas Instruments, MediaTek, Samsung …

Shamitha Rao, Intel

Shamitha Rao : Shamitha Rao is SOC Design Eng Manager, Design for Test in Super Computing Platform group at Intel. Shamitha is currently leading end to end DFT implementation and validation on complex SoCs while actively mentoring multiple DFT engineers to achieve excellence in DFT execution. Shamitha has over 18 years of experience in DFT, with expertise ranging from creating best in class flows for DFT implementation/validation to defining and implementing DFT solutions to cater to customer/design needs and end to end DFT execution on complex designs. Prior to taking up her role in Intel, she has been associated with companies like Siemens, STMicroelectronics, Wipro Technologies. She holds a bachelor’s degree in Electronics and Communications from Kuvempu University. She has co-authored several papers and publications, tutorials in multiple technical forums such as ITC, ATS etc.

Tutorial Summary: (Abstract)

The objective of this tutorial is to provide valuable information and make a conscious attempt to explain the basic concepts of Design For Test (DFT) through examples and illustrations. This tutorial also helps to map theoretical DFT knowledge gained from academics to the actual DFT application during various phases of SoC development and life cycle. This tutorial aims to focus on introducing various DFT techniques and implementation methods used in System On Chip(SoC) Life Cycle with emphasis on the popular methods used for digital logic and memory testing. This includes explaining DFT techniques used to screen various defects on Silicon before shipping to the customer, as well details of design infrastructure required for enabling the same. We will also provide insights to various nonstandard techniques that are used for special components in SOC like IOs/Analog etc. We will take a glance at special requirements for Automotive SoCs. In conclusion, we will introduce to Design for test techniques for yield improvement and debug that is used in the industry.

Tutorial 4

Title: “Error Resilient AI System: Addressing Soft Errors, Security, Threats and Manufacturing Variability Effects“

Speakers:

  • Abhijit Chatterjee, Georgia Tech, USA

Biographies of the presenters:

Abhijit Chatterjee, Georgia Tech, USA

Abhijit Chatterjee is a Professor in the School of Electrical and Computer Engineering at Georgia Tech and a Fellow of the IEEE. He received his Ph.D in electrical and computer engineering from the University of Illinois at Urbana-Champaign in 1990. Dr. Chatterjee received the NSF Research Initiation Award in 1993 and the NSF CAREER Award in 1995. He has received seven Best Paper Awards and three Best Paper Award nominations. His work on self-healing chips was featured as one of General Electric’s key technical achievements in 1992 and was cited by the Wall Street Journal. In 1995, he was named a Collaborating Partner in NASA’s New Millennium project. In 1996, he received the Outstanding Faculty for Research Award from the Georgia Tech Packaging Research Center, and in 2000, he received the Outstanding Faculty for Technology Transfer Award, also given by the Packaging Research Center. In 2007, his group received the Margarida Jacome Award for work on VIZOR: Virtually Zero Margin Adaptive RF from the Berkeley Gigascale Research Center (GSRC). Dr. Chatterjee has authored over 450 papers in refereed journals and meetings, has 22 patents and supervised over 50 Ph.D dissertations. He is a co-founder of Ardext Technologies Inc., a mixed-signal test solutions company and served as chairman and chief scientist from 2000-2002. His research interests include error-resilient machine learning, signal processing and control systems, mixed-signal/RF/multi-GHz design and test and adaptive real-time systems.

Tutorial Summary: (Abstract)

The reliability of emerging neuromorphic compute fabrics is of great concern due to their widespread use in critical data-intensive applications. Ensuring such reliability is difficult due to the intensity of underlying computations (billions of parameters), errors induced by low power operation and the complex relationship between errors in computations and their effect on network performance accuracy. In this tutorial, we study the problem of designing error-resilient neuromorphic systems where errors can stem from: (a) soft errors in computation of matrix-vector multiplications and neuron activations, (b) malicious trojan and adversarial security attacks and (c) effects of manufacturing process variations on analog crossbar arrays that can affect DNN accuracy. The core principle of error detection relies on embedded predictive neuron checks using invariants derived from the statistics of nominal neuron activation patterns of hidden layers of a neural network. Algorithmic encodings of hidden neuron function are also used to derive invariants for checking. A key contribution is designing checks that are robust to the inherent nonlinearity of neuron computations with minimal impact on error detection coverage. Once errors are detected, they are corrected using probabilistic methods due to the difficulties involved in exact error diagnosis in such complex systems. The technique is scalable across soft errors as well as a range of security attacks. The effects of manufacturing process variations on analog accelerators are handled through the use of compact tests from which DNN performance can be assessed using learning techniques. Postmanufacture tuning is performed to improve yield by as much as 40%. Experimental results on a variety of neuromorphic test systems: DNNs, spiking networks and hyperdimensional computing are presented.

Tutorial 5

Title: “Guaranteeing quality in automotive EMC tests through in-house EMC test“

Speakers:

  • George Thottan, Texas Instruments
  • Rajesh Chauhan, Texas Instruments
  • Dilip Jain, Texas Instruments

Biographies of the presenters:

George Thottan, Texas Instruments

George Thottan, Validation Manager, Power Switches, Analog Power Products George joined TI in 2016. He holds a Master’s degree in Electronics Design Technology. He had been the lead validation engineer across multiple automotive products across different TI portfolios like High Side controllers, Ideal diode controllers and High Side switches. He was the technical lead for a team which worked to establish an inhouse EMC set up in TII.

Rajesh Chauhan, Texas Instruments

Rajesh Chauhan, Validation Manager, Motor Drives, Analog Signal Chain Rajesh Chauhan joined TI in 2016. He holds a Master’s degree in Communication system. He had been the lead validation engineer across multiple Industrial and Automotive products across different TI portfolios like Transceivers, Mux and Switches and Motor drives. He is currently the part of team which working to establish an inhouse component level EMC set up in TII.

Dilip Jain, Texas Instruments

Dilip Jain, Systems Manager, Power Switches, Analog Power Products Dilip Jain is responsible for roadmap development and defining products such as Ideal Diode controllers and 100V smart high side controllers. He was elected to MGTS tech ladder title in 2021. He has 14 years of broad experience in power management domain with expertise in power supply design and circuit protection for Automotive and Industrial power. He holds a master’s degree in Electrical Engineering from the Indian Institute of Technology, Bombay.

Tutorial Summary: (Abstract)

 Automotive industry is very safety critical, as any component failure in an automobile subsystem can lead to accidents and even loss of life. Automotive electronics today is in a fast-growing trajectory and is a major market where semiconductor industry focuses its resources. Automotive electronics has unique set of problems given the solution density and harsh operating environment. This extremely competent industry subjects all electronic subsystems to extensive Electromagnetic compatibility (EMC) tests to ascertain quality and reliability. These tests are highly resource and time intensive. Current market philosophy drives to incorporate a “Design for EMC” approach to identify EMC problems upfront to address them early in the design stages to minimize cost and cycle time. This strategy requires robust EMC checks at component level prior to a subsystem or vehicle level checks. It opens up a completely new domain of tests under silicon validation for automotive IC’s. This calls for better understanding of EMC tests by validation engineers to perform quality assessment of products. This tutorial outlines firsthand how such an initiative in Silicon validation has brought out significant impact in terms of winning shares and leading the market. This insight becomes even more relevant as the industry views automotive market as the roadmap for growth

Tutorial 6

Title: “Power Domains and Physical Synthesis – A DFT Perspective“

Speakers:

  • Sarthak Singhal, Cadence
  • Subhasish Mukherjee, Cadence
  • Dr. Krishna Chakravadhanula, Cadence
  • Bharath Nandakumar, Cadence

Biographies of the presenters:

Sarthak Singhal, Cadence

Sarthak is working as Sr. Principal Product Engineer for Modus DFT Software Solutions at Cadence Design Systems. He has over 10 years of industry experience. His focus includes DFT architectures and methodologies. He is responsible for augmenting Cadence DFT and ATPG tools by deploying, architecting and supporting new TEST methodologies and flows across customers. He has published four IEEE conference papers in India & US. He graduated from NIT, Allahabad majoring in Electronics and Communication Engineering in 2012.

Subhasish Mukherjee, Cadence

Subhasish is a passionate learner and has a penchant to find viable solutions to software and hardware complexities. He has resound interest in designing large scale complex software that is used in DFT and EDA in general. Subhasish has been a key developer of many complex features of Cadence DFT product base. He is working as a Software Engineering Director and is leading the Cadence DFT development activities in India.

Subhasish holds a Master’s degree in Computer Science & Engineering and has 25 years of industry experience. He received multiple organizational awards at Cadence, holds multiple US patents, authored several papers in IEEE conferences and international journals and was session chair at different national and international VLSI and Test conferences.

Bharath Nandakumar, Cadence

Bharath is Principal Software Engineer in Modus DFT Software Solution R&D group at Cadence Design Systems, Noida. He manages the Diagnostics and User Interface team. His 6+ years of experience at Cadence involves working on multiple research projects to enhance the Modus software, resulting in multiple publications. He is an active member of ITC India 2022, 2023 committee. He received his Master’s degree in VLSI Design Tools & Technology from Indian Institute of Technology, Delhi.

Tutorial Summary: (Abstract)

Power and Physical awareness has become an important dimension for recent advances in VLSI. Physical synthesis, the integra*on of logic synthesis with physical design informa*on, was born in the mid to late 1990s. Fast forward to 2023, It is the de-facto implementa*on approach for any modern mid or large sized SoC. Unified Power Format (UPF) is the popular name of the Ins*tute of Electrical and Electronics Engineers (IEEE) standard for specifying power intent in power op*miza*on of electronic design automa*on published in 2009. Along with physical synthesis, UPF is also a must have for low power SoCs specifically for IoT and automo*ve applica*ons. With increasing power demands in modern SoCs, a lot of academic & industrial research is done to design macros opera*ng in mul*ple low power modes depending upon the voltage value of each supply. Mul*ple func*onal power domains (PD) are forcing Design-for-Test (DFT) designers to adjust DFT inser*on and implementa*on to comply with IEEE 1801 correctness. Several challenges emerge for DFT tools and engineers, including but not restricted to a) addi*onal low power cells inserted & crossings created due to DFT connec*ons, b) power aware scan chain connec*on with op*mal scan wirelength, and c) ensuring Unified Power Format (UPF) correctness post DFT inser*on. As the design community moves to the complete adop*on of a physical synthesis flow, it is becoming evident that test synthesis must be cognizant of layout issues and well-integrated within physical design tools. By bringing in key physical func*ons into the front-end of the DFT physical synthesis flow, the designer can successfully meet all design and testability goals, with minimum impact on *ming closure. At the end of this tutorial, attendees would be able to understand the issues & challenges that arise while doing power & physical domain aware DFT implementation. They would also learn how to mitigate those channels & modification required in DFT flows to enable them for physical & power domain awareness. The tutorial is divided into two parts, one for UPF based DFT implementation & other about physical aware DFT.

Tutorial 7

Title: “Hierarchical and tile based DFT techniques for AI and Large SoCs“

Speakers:

  • Lee Harrison, Siemens EDA
  • Peter Orlando, Siemens EDA

Biographies of the presenters:

Lee Harrison, Siemens EDA

Lee Harrison is Product Marketing Director, with the Tessent product division at Siemens EDA. He has over 20 years of industry experience with Mentor DFT products and has been involved in the specification of new test features and methodologies for Mentor customers, delivering high quality DFT solutions. With a focus on Automotive, Lee is working to ensure that current and future DFT requirements of Mentor’s Automotive customers are understood and met. Lee Received his BEng in MicroElectronic Engineering from Brunel University London in 1996. Lee presents regularly at industry conferences such as DAC, ITC, VTS, ETS, DATE etc.

Peter Orlando, Siemens EDA

Peter is the SSN Product manager and part of the Siemens Tessent DFT Product Marketing team. Since joining Siemens 2018, Peter has been part of the development of SSN product and primarily responsible of the deployment of SSN. As the customer facing technical lead for the SSN product, Pete has been providing implementation guidance to external customers and internal colleagues. He’s been part of many designs that have successfully taped out with SSN. Pete’s role in SSN continues to expand with the development and deployment of new features being added to regularly.

Prior to joining Siemens, Pete has worked in the silicon industry for 29 years, with most of that time in the field of DFT, for such companies as Marvell Semiconductor, Micron Technology, ST Microelectronics, and LSI logic.

Tutorial Summary: (Abstract)

In this tutorial, we will proceed to give an overview of the exciting field of AI and HPC. It will cover the critical and special characteristics and the architecture of the popular AI chips. Next we will summarize the features of the AI chips from design-for-test (DFT) perspective and introduce the DFT technologies that can help testing AI chips. We will also look at how the shift to 2.5D and 3D including Chiplet development is changing the industry and the adding new challenges for the DFT community Finally, we will present a few case studies on how DFT is implemented in the real AI chips. We will also present some of the functional monitoring techniques that are available today. An overall architecture showing how functional monitoring can be implemented and how the monitor data can be used to manage in-life capabilities. Finally, we will present a few case studies on how DFT is implemented in the real AI chips.

Tutorial 8

Title: “Hardware Security: A perspective towards Fault Analysis Vulnerabilities“

Speakers:

  • Bodhisatwa Mazumdar, IIT Indore

Biographies of the presenters:

Bodhisatwa Mazumdar, IIT Indore

Dr. Bodhisatwa Mazumdar is an Associate Professor in the Department of Computer Science and Engineering, and Associate Dean-R&D II, at IIT Indore. He earned his M.S. and Ph.D. degrees from the Indian Institute of Technology (IIT) Kharagpur, Kharagpur, India. He was a Postdoctoral Researcher with the Design for Excellence Laboratory, New York University Abu Dhabi, Abu Dhabi, UAE. His current research interests include optimized hardware implementations of cryptographic primitives, and side channel attacks and countermeasures. He is presently a voting-cum working group member (WGM) in IEEE Standard 1413.1 on Guide for Selecting and Using Reliability Predictions, and IEEE 1624, which is the IEEE Standard for Organizational and Capability. He has received Early Career Research Award from CSIR, New Delhi. Dr. Mazumdar has been a Technical Program Committee Member of conferences, such as VLSID, SPACE, and VDAT, and is one of the Program Chairs of SPACE 2023 conferences.

Tutorial Summary: (Abstract)

In this tutorial, we focus on hardware security aspects that exist in the present-day IC industry. The tutorial will mainly focus on different types of fault analysis attacks that bother ICs and their security applications when deployed in field. Over the past decade, IoT devices are becoming more ubiquitous, and are often exposed to attacks that are device specific. One such class of attacks is fault attack. With unprecedented level of embedded technology and device connectivity, security an privacy of user data has emerged as paramount importance. In general, secure computations through the use of cryptographic modules has been the primary mechanisms to alleviate such concern. However, crypto-processors that implement such modules have themselves been subjected to implementation attacks, such as sidechannel and fault injection analysis. Given the fact that a large number of embedded devices are significantly resource-constrained with low processing power and memory availability, provably-secure and mathematically robust lightweight cryptographic architectures and constraints do exist in literature. However, security in theory is more often different from practice, with many a sip between the cup and the lip. One such sip that we will focus on are implementation-based attacks on embedded devices with the ability to weaken even cryptographic primitives that cater to world-wide standard specifications. A fault once injected in such an IC, can modify or skip the sequence of instructions, modify or erase data, access non-permitted memory location or perform a non-permitted operation, 1 and skip certain countermeasures. The present research trends show that the wide usability and practicality, lightweight computations and attacker’s simulation capabilities of exploiting the spatio-temporal characteristics of the fault often render such attacks powerful. In this tutorial, we will focus on fault analysis attacks or fault injection attacks with a comprehensive outlook on future research directions that follow from the discussions during the presentation.

Tutorial 9

Title: “Power Aware DFT“

Speakers:

  • Karthik Natarajan, Synopsys
  • Likith Manchukonda, Synopsys
  • Manish Arora, Synopsys
  • Rahul Singhal, Synopsys
  • Greeshma Jayakumar, Synopsys

Biographies of the presenters:

Karthik Natarajan, Synopsys

Karthik Natarajan is a Director in Synopsys Test group. He has more than 14 years of experience in Design for Test from Architecting DFT for complex SoC’s to Silicon Bringup & Yield Ramp. He has multiple patents and papers in the field of Test.

Likith Manchukonda, Synopsys

Likith Manchukonda is a Sr. Solutions Engineer in Synopsys Test group. He has more than 7 years of combined experience in CAD, circuit design and in DFT from test architecting to silicon bringup.

Manish Arora, Synopsys

Manish Arora is a Sr. Solutions Manager in Synopsys Test group. He has 16 years of experience in DFT with prominent companies like Freescale and AMD. He has a broad experience in memory test and repair for various end applications like automotive, mobile and CPU/GPU designs.

Rahul Singhal, Synopsys

Rahul Singhal is a Product Manager for TestMAX DFT, ATPG and Test-AI products at Synopsys. His focus is on the industry requirements and solutions in the areas of test compression, test streaming solutions and ATPG. He has co-authored multiple tutorials, papers, posters on test in leading IEEE conferences. Rahul received his MS in Electrical Engineering from Portland State University and BS in Electrical Engineering from Purdue University.

Greeshma Jayakumar, Synopsys

Greeshma Jayakumar is a Staff Application Engineer in Synopsys Test Group where she is leading the India regional customer support on the Synopsys TestMAX family of products. She has overall 11 years of experience in the DFT industry and has worked on test architecture, methodology, ATPG & Silicon bring up.

Tutorial Summary: (Abstract)

Power Handling during Test is an important factor that needs to be considered during chip design, silicon bring-up, and In-System Testing. In this tutorial, we will start by listing the importance of power and the different problems faced with poor power intent. We will then proceed to give an overview of different power aspects related to test, from RTL implementation to in-system validation, and how each step can impact the overall performance. Next, we will introduce the different DFT techniques for design that help with better power planning producing optimized quality of results (QoR). Finally, we will present data sets on how each of the listed techniques implemented on real designs give the desired results. This tutorial will include the following three parts (each part will be 20 minutes): Memory and Scan Test Implementation, Scan Synthesis, Placement and Routing, Automatic Pattern Generation

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