Posters

Title Authors
Divide And Concur the Scan World of Mammoth SoCs with Novel Pattern Porting Approach Bharat Londhe, Akhtar Tamboli, Mayur Gavali, Pradeep Nagalapura
Debugging Scan Chain Hold Timing Violations with the Voltage BUMP Feature of ATE Vinay Kumar and Bhrugurajsinh Chudasama
Generic methodology for emulation and test of a USB-PD Source Shubha T R, Biju Erayamkot Panayamthatta and Mahadev G
Advanced Test Clock Generator (ATCG) to reduce the Pattern count and Improve the test Coverage Shivasharanappa Biradar, Sneha Revankar and Abhinand Sk
An Adaptive Novel approach for SCAN Safety Sealing Checker in Pre-Silicon Sudheer Anumala and Rajni Jain
Algorithm to translate natural language based test case to BDD based test case Chandrashekhar Bhatta and Divya A L
Partition-level Boundary Scan re-use as is for SoC – shift left of Boundary Scan content bring up and validation Prashant Sonone
Efficient Way of TPI for Pattern Optimization Arindam Pratul Sarma, Deepen Talati and Savan Bhatelia
Droop compensation method in System Vmin measurement Manjunath M R, Priyanka Sharma and Asaf Hay
Locating Faulty Memristors For Solving Sneak Path Problem in Memristive Crossbars Aishwarya Deb, Subhadip Maji, Sanandita Das, Pooja Joshi and Hafizur Rahaman
Enhanced DVS Flow for Attaining Highest Quality SoCs Dharani Kumar Srinivasan, Mahesh Kumar M K and Praveen Raghuraman
On Board(IoB), ATE Solution & Implementation challenges for Ultra Low IB Measurements for Op-Amp Aravind Lijoy and Bikash Gupta
An Area and Test-time Comparative Study On TAP and SIB based Networks In MBIST Nadeem Pasha Mohammad, Mohit Mathur and Keerthana M
Securing the test infrastructure from FSA attack M Prathiba and S Sivanantham
SOC Methodology for boundary conditions validation Meghana L, Sreenivasa Rao Vuttaravilli and Tushar Jeevan
An Efficient Memory Grouping Methodology for MBIST Tarun Goyal, Puneet Arora and Carl Wisnesky
ATPG driven masking of user specified channels Vaibhav Mishra, Aenikapati Swetha Priya, Sahil Narang, Bharath Nandakumar and Sameer Chillarige
Hierarchical Test Flow for Large SoC’s Vatsal Grover, Sarthak Singhal, Prashant Narang, Kapil Juneja and Khushboo Yadav
A comprehensive approach towards compact test pattern set generation for Small Delay Defects Priyanka Bhatt, Leela Krishna Thota, Sreenivasarao Vuttaravilli and Sravan Kumar Challa
Burn-in and ATE Stress tests: Significance and Challenges in Post Silicon Cycle Abhishek Bhattacharya and Ananthashayana M S
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