Keynotes

Keynote 1

Title: “Can Structural Test play a role in mitigating Silent Data Errors?“

Speaker:

Nilanjan Mukherjee, Siemens EDA

Bio:
Nilanjan Mukherjee is a Senior Director of Engineering for Tessent Silicon Lifecyle Solutions at Siemens EDA. He has been actively involved in the R&D of key technologies in the areas of test quality, test compression, Logic BIST, Memory BIST, low power DFT, and diagnosis. Specifically, he was involved in the development and productization of EDT/TestKompress, the VersaPoint Test Points technology, a Low Power Hybrid EDT/Logic BIST scheme for automotive ICs, and Observation Scan Technology for Logic BIST. More recently his focus is on developing new in-system/in-field test solutions based on deterministic patterns (In-system TestKompress) including silicon lifecycle management for automotive and data-center markets.
Nilanjan has co-authored more than 90 technical papers and is a co-inventor of 56 US patents and several international patents. He has received numerous awards including Best Paper Awards at VTS 2020, VLSI Design 2009, ATS 2001, and VTS 1995, the Most Significant Paper Award at ITC 2012, Siemens DISW Invention of the year 2019, and the Donald O. Pederson Outstanding Paper Award in 2006.
Nilanjan received a Ph.D. degree from McGill University, Canada. Nilanjan has given numerous tutorials, short-term courses, and invited talks at premier IEEE/ACM conferences, symposia, universities, and companies across the world.

Abstract:
The evolution and continuous growth of data-intensive applications such as AI/ML, IoT, blockchain, etc. have fueled the rise of hyperscale datacenters across the world (including India). It is forecasted that the number of such hyperscale datacenters will exceed one thousand by 2026 (Synergy Research Group). One of the biggest challenges facing such hyperscale datacenters is Silent Data Error (a.k.a. Silent Data Corruption). Silent Data Error (SDE) is an industry-wide phenomenon that not only impacts memories, storage, and networking but also CPUs. Technology scaling, system scaling, increased density, and wide data-paths have been identified as key contributors to such errors. SDE tends to be very elusive as it is not traceable at the hardware level but manifests as an application-level problem with potentially devastating impact on datacenter reliability and availability. More importantly, such failures occur at specific environmental conditions (power, temperature, and voltage profiles) in a system running applications creating targeted software workloads. In recent years, there has been a lot of discussion emphasizing the role of manufacturing test escapes on SDE. Additional factors such as design marginalities, latent/intermittent defects, and transistor aging potentially also impact the behavior of silicon in-field. In this talk, we will explore how structural test can play an important role in alleviating Silent Data Error. We will not only look at ways to improve test quality, but also highlight a hierarchical, scalable, and adaptive DFT infrastructure, needed for various phases of test including continuous monitoring of electronic devices throughout the silicon lifecycle.

Keynote 2

Title: “Test industry challenges and solutions as observed by the leading physical implementation solution provider“

Speaker:

Janet Olson, Cadence

Bio:
Janet Olson is Vice President Research and Development for Front-End Design at Cadence Design Systems. Janet is responsible for Modus, Cadence’s IC test solution, high level synthesis (Stratus) and constraint verification (Litmus).  Janet has a master’s degree in Electrical Engineering from Stanford and a bachelor’s degree from CMU and holds 7 US patents. Janet has been recognized with the 2017 Marie R. Pistilli Electronic Design Award and the 2016 YWCA Tribute to Women award.

Abstract:
Test is a mission critical aspect of the design process, but design functionality/verification consumes the significant majority of engineering focus, with test often retrofitted late in the design cycle. The era of point-tools is over, what’s needed is deep collaboration across the flow from state-of-the-art design IP, verification, physical design, and packaging. New solutions must manage test structures from multiple sources and meet coverage, test time, and PPA goals without introducing design closure iterations. This presentation offers a new way forward, borne from Cadence’s unique perspective gained from experience working with global semiconductor suppliers engineering test into some of the world’s most complicated designs.

Keynote 3

Title: “Disruptive Technologies Drive a New Era of Test“

Speaker:

Fadi Maamari, Synopsys

Bio:
Fadi Maamari is Vice President of Engineering in the Hardware Analytics and Test group of Synopsys, responsible for the TestMAX Product line. He joined Synopsys in the 2015 acquisition of Atrenta, where he was Chief Product Architect. He was previously VicePresident of Engineering and COO of LogicVision when it was acquired by Mentor in 2009. Fadi has a Ph.D. in Electrical Engineering from McGill University in Montreal, and started his career at AT&T Bell Labs working on various EDA algorithms and Design For Test

Abstract:
The semiconductor test community is facing multiple challenges driven by the ever-growing performance and reliability expectations of today’s cutting-edge technology. Modern designs have increased test coverage, quality and accuracy requirements and mounting test costs mean even more pressure to reduce time on the tester. Leveraging disruptive technologies, such as unlimited compute and AI capabilities is the key to providing solutions to these challenges, unlocking a whole new era of test capabilities and efficiencies.
This keynote will explore two fundamental areas where disruptive technologies are already starting to have a positive impact on semiconductor test. Firstly, Time to Results (TTR) is a critical factor when it comes to successfully scaling the design cycle and these latest developments are allowing test engineers to implement test time reductions while maintaining high levels of quality and performance. Secondly, advances in AI have enabled much higher quality test pattern generation and this is already proving beneficial as part of a solution to address new industry challenges such as Silent Data Corruption (SDC), where undetected hardware logic failures can result in incorrect data results.
These advancements in combination with the emerging paradigm of Silicon Lifecycle Management (SLM) are signaling a new era of Semiconductor Test.

Keynote 4

Title: “Paradigm Shift: Structural Approaches to Analog and RF Test“

Speaker:

Sule Ozev, Arizona State University

Bio:
Sule Ozev obtained her B.S. degree in Electrical Engineering from Bogazici University, Turkey in 1995, and her Ph.D. in Computer Science and Engineering from UC San Diego, USA in 2002. She has been a faculty member, first at Duke University and then at Arizona State University since 2002. Her research interests include test methods, statistical test metrics, and built-in test for analog/RF circuits as well as MEMS devices. She has published over 200 papers in this domain and has won 8 best paper and honourable mention awards at various IEEE conferences. She holds 4 US patents.

Abstract:
Analog and RF test has been considered to be a niche domain where test patterns are developed based on experience of the test engineer and specifications of the product. This approach worked well particularly when analog and RF circuits have been implemented by mature processes where defect rates were better controlled. Even then, this ad-hoc testing process leaves the IC vendors with no quantitative metric of defect defect coverage and no recourse if testability becomes a major bottleneck for time-to-market. Seemingly endless integration of system components, including RF devices on a single die or package requires a paradigm shift for testing analog and RF devices. Structural approaches to testing, built-in test, and test quality metrics are needed. This presentation provides a historical context for structural test efforts as well as provide a sneak peek into the future of structural testing and test quality metrics in the analog domain.

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