Tutorial Program

Sunday, July 18, 2021
8:30 am – 9:30 am
Session Chair: Anurag Jain
Session Chair: Shamitha Rao
Session Chair: Kavitha Shankar
Zoom Meeting
Zoom Meeting
Zoom Meeting
9:30 am – 11:00 am
(15 mins. Break)
11:15 am – 12:45 pm

T1 : Identifying Good, Bad and Ugly chips through DFT : A Primer on VLSI Testing

Abhishek Chaudhary
(Texas Instruments India)

T2 : Advanced DFT and Security Technology for AI chips

Lee Harrison, Peter Orlando,
Jay jahangiri
(Siemens EDA)

T3 : Addressing Test, Safety and Security for Connected Automotive IC’s

Gajinder Panesar, Nilanjan Mukherjee, Raghav Mehta, Lee Harrison
(Siemens EDA)
Nir Sever, Gal Carmel (protean Tecs)
12:45 pm – 1:45 pm
1:45 pm – 3:15 pm
(15 mins. Break)
3:30 pm – 5:00 pm

T4 : Testing Power and Clock Networks

Prof. Shi-Yu Huang (Professor, Faculty of Electrical Engineering Department, National Tsing Hua University, Taiwan)

T5 : Device-Aware-Test for Emerging Memories: The means to win the war against unmodeled faults

Said Hamdioui (Delft Universitty of Technology)

T6 : New Directions in Semiconductor Test and Validation

Dr. C P Ravikumar (Texas Instruments India)

Tutorial 1:

Title: "Identifying good , bad and ugly chips through DFT : A primer on VLSI testing"

Abhishek Chaudhary


           Abhishek Chaudhary is an experienced DFT Engineer with 14 years of experience in the semiconductor industry. He is presently working at Texas Instruments Bangalore. Prior to joining TI, he led the team of engineers that owned DFT for all IPs, testchips and bufferchip ASIC designs developed worldwide at Rambus. Prior to Rambus, Abhishek worked at Freescale Semiconductor where he worked primarily on DFT for automotive chips.
Abhishek has a passion for continued education and has been an active participant in IEEE TTTC events and has presented on DFT topics at various external events and conferences.
Abhishek holds a Master’s degree from IIT Delhi and Bachelors from Visvesvaraya National Institute of Technology, Nagpur.

Tutorial 2:

Title: "Advanced DFT and Security technologies for AI Chips"

Jay Jahangiri


       Jay Jahangiri is a Product Manager for Tessent products at Siemens EDA (Siemens Digital Industry Software). He has over 25 years of experience in various DFT disciplines including ATPG, compression, BIST, and boundary scan. Jay worked as a DFT engineer for Texas Instruments and Raytheon prior to joining Siemens EDA. He is the co-inventor of two US patents related to silicon test and holds a Bachelor of Science degree in Electrical Engineering and an MBA. Jay has published numerous papers and articles in the area of silicon test.

Lee Harrison


           Lee Harrison is Automotive IC Test Solutions Manager, at Siemens EDA. He has over 20 years of industry experience with Tessent DFT products and has been involved in the specification of new test features and methodologies for Siemens customers, delivering high quality DFT solutions. With a focus on automotive, Lee is working to ensure that current and future DFT requirements of Siemens’s automotive customers are understood and met. Lee received his BEng in MicroElectronic Engineering from Brunel University London in 1996.

Peter Orlando


          Peter has been working for Siemens in Wilsonville, Oregon since June 2018 as a member of Tessent DFT products division. During his time at Siemens, he has been focusing on the development and deployment of the Streaming Scan Network (SSN) product. Prior to joining Mentor, Peter has worked in the silicon industry for 25 years for such companies as Marvell Semiconductor, Micron Technology, ST Microelectronics, and LSI logic.

Tutorial 3:

Title: "Addressing Test, Safety and Security for Connected Automotive ICs"

Gajinder Panesar


           Gajinder Panesar is a Fellow at Mentor, A Siemens Business. One of Europe’s leading SoC architects, Gadge’s experience includes senior architecture definition and design roles within both blue-chip and start-up environments. He holds more than 50 patents and is the author of more than 20 published works. Gajinder was CTO at UltraSoC prior to the company’s acquisition by Mentor-Siemens. He has also held roles at NVIDIA (NASDAQ:NVDA); and Picochip, where he was Chief Architect, a role in which he continued after the company’s acquisition by Mindspeed Inc (NASDAQ:MSPD). His previous experience includes roles at STMicroelectronics, INMOS, and Acorn Computers. He is a former Research Fellow at the UK’s Southampton University, and a former Visiting Fellow at the University of Amsterdam.

Nilanjan Mukherjee


          Nilanjan Mukherjee is a Senior Engineering Director for Tessent Silicon Lifecycle Solution Division at Siemens Digital Industries Software (DISW). He has been with Siemens (previously Mentor) for almost two decades, where he is involved in the research and development of key technologies in the areas of test compression, Logic BIST, Memory BIST, low power DFT, and memory test/diagnosis. Some of his major accomplishments include being a co-inventor and an architect of the Embedded Deterministic Test (EDT) technology, the VersaPoint Test Points technology, a Low Power Hybrid EDT/Logic BIST scheme for automotive ICs, and the Observation Scan Technology for Logic BIST. Currently, his focus is on developing new solutions and methodologies for improving the quality and reliability of automotive ICs. Prior to joining Mentor Graphics, he worked at Lucent Bell Laboratories in New Jersey.

          As a researcher, Nilanjan has co-authored more than 85 technical papers for various conference proceedings and archival journals. He is a co-inventor of 52 US patents and several international patents. He has received numerous awards and recognition including the Best Paper Award at VTS 2020, Siemens Digital Industries Software Invention of the year 2019, the Most Significant Paper Award at ITC 2012, the Best Paper Award at VLSI Design in 2009, the Donald O. Pederson Outstanding Paper Award from the IEEE Circuits and Systems Society in 2006, the Teruhiko Yamada Memorial Best Student Paper Award at ATS 2001, and the Best Paper Award at VTS 1995. Nilanjan received a B.Tech. (Hons) degree from IIT, India, and a Ph.D. degree from McGill University, Canada. He has given numerous tutorials and invited talks at DAC, ITC, VTS, ATS, and VLSI Design, and has offered many short term courses on DFT.

Raghav Mehta


           Raghav Mehta is Technology Enablement Engineer at Siemens. He specializes in automotive DFT implementation. Over last couple of years, he has focused on consulting efficient flow methodology for automotive ICs. At Siemens, Raghav has co-created custom MBIST solution for various different memories. His work focuses on memory testing, built in test technologies for logic and memory and DFT for automotive. Raghav achieved his MS degree in VLSI system design from University of Southern California, United States

Lee Harrison


           Lee Harrison is Automotive IC Test Solutions Manager, at Siemens EDA. He has over 20 years of industry experience with Tessent DFT products and has been involved in the specification of new test features and methodologies for Siemens customers, delivering high quality DFT solutions. With a focus on automotive, Lee is working to ensure that current and future DFT requirements of Siemens’s automotive customers are understood and met. Lee received his BEng in MicroElectronic Engineering from Brunel University London in 1996.

Gal Carmel


          Gal Carmel, EVP, GM Automotive, proteanTecs. An Automotive and Product entrepreneur with a proven track record of over 15 years in rapidly honing emerging technologies, markets and opportunities, both on business and diverse R&D aspects. Before joining proteanTecs, Gal served as Chief Technology and Production Engineering of Samsung Smart Machines, building from the ground-up Samsung’s ADAS/AV technology, focusing on full-stack platforms for automated driving systems. Prior to that, he held key roles in some of the most innovative pillars of autonomous driving at Mobileye (acquired by Intel), a leading supplier of Advanced Driver Assist Systems (ADAS). In 2016, Gal brought up Mobileye’s Road Experience Management (REM) technology for data harvesting and localization engine, enabling full autonomy. And in 2013, he brought to production its first Mono Vision Camera AEB (Autonomous Emergency Braking), reaching 5 Star Euro NCAP rating for the most advanced production programs OEMS (Audi, BMW, Nissan). Gal holds a BSc in Electrical Engineering from Tel Aviv University.

Nir Sever


      Nir Sever is an industry veteran with over 30 years of technological and managerial experience in advanced VLSI engineering. Before joining proteanTecs, Nir served for 10 years as the COO of Tehuti Networks, a pioneer in the area of high-speed networking Semiconductors. Prior to that, he served for 9 years as Senior Director of VLSI Design and Technologies for Zoran Corporation, a recognized world leader in Semiconductors for the highly competitive Consumer Electronics market. Nir was responsible for driving Zoran’s silicon technologies and delivering more than 10 new silicon products each year. Prior to that, Nir held various managerial and technological VLSI roles at 3dfx Interactive, GigaPixel Corporation, Cadence Design Systems, ASP Solutions, and Zoran Microelectronics. Nir holds a B.Sc in Electrical Engineering from The Israel Institute of Technology, Technion.

Tutorial 4:

Title: "Testing Clock and Power Networks"

Shi-Yu Huang


      Shi-Yu Huang received his Ph.D. degree in Electrical and Computer Engineering from University of California, Santa Barbara, in 1997. Since 1999, he has joined National Tsing Hua University, Taiwan until now. He recent research is concentrated on all-digital timing circuit designs, such as all-digital phase-locked loop (PLL), all-digital delay-locked loop (DLL), time-to-digital converter (TDC), and their applications to parametric fault testing and reliability enhancement for 3D-ICs. He has published more than 160 refereed technical papers. Dr. Huang ever co-founded a company in 2007-2012, TinnoTek Inc., specializing a cell-based PLL compiler and system-level power estimation tools. He received the best-presentation award or best-paper awards from several IEEE technical meetings, (i.e., VLSI-DAT’2006, VLSI-DAT’2013, ATS’2014, WRTLT’2017, ISOCC’2018). He is a senior member of IEEE.

Tutorial 5:

Title: "Device-Aware-Test for Emerging Memories: The means to win the war against unmodeled faults"

Said Hamdioui


    Hamdioui is currently Chair Professor on Dependable and Emerging Computer Technologies, Head of the Quantum and Computer Engineering department, and also serving as Head of the Computer Engineering Laboratory (CE-Lab) of the Delft University of Technology, the Netherlands. He is also co-founder and CEO of Cognitive-IC, a start-up focusing on hardware dependability solutions and consultancy.

         Hamdioui received the MSEE and PhD degrees (both with honors) from TUDelft. Prior to joining TUDelft as a professor, Hamdioui spent about seven years within industry including Intel Corporation (Califorina, USA), Philips Semiconductors R&D (Crolles, France) and Philips/ NXP Semiconductors (Nijmegen, The Netherlands). His research focuses on two domains: emerging technologies and computing paradigms (including memristors, in-memory-computing, neuromorphic computing, low power HW architecture for edge AI, etc.), and hardware dependability (including Testability, Reliability, Hardware Security).

         Hamdioui owns many patents, has published one book and contributed to other two, and had co-authored over 250 conference and journal papers. He has consulted for many worldwide leading semiconductor companies . He is strongly involved in the international community as a member of organizing committees or a member of the technical program committees of the leading conferences. He delivered dozens of keynote speeches, distinguished lectures, and invited presentations and tutorial at major international forums/conferences/schools and at leading semiconductor companies. Hamdioui is a Senior member of the IEEE, Served as Associate Editor of IEEE Transactions on VLSI Systems (TVLSI) [215-2018], Journal, the Journal of Electronic Testing: Theory and Applications (JETTA) [2011-2019], Elsevier Microelectronic Reliability [2019-2020]; and he serves on the editorial board of IEEE Design & Test, and ACM Journal on Emerging Technologies in Computing (JETC). He is also member of AENEAS/ENIAC Scientific Committee Council (AENEAS =Association for European NanoElectronics Activities). He is also EEE Circuits and Systems Society (CASS)Distinguished Lecturer.

         Hamdioui is the recipient of many international/national awards. E.g., he is the recipient of European Design Automation Association Outstanding Dissertation Award 2001; European Commission Components and Systems Innovation Award in 2020; the 2015 HiPEAC Technology Transfer Award; and many Best Paper Awards (DATE’20, ICCD’15, LATS’18, DTIS’15, IVLSI’16, FCST’17); Teacher of the Year Award at the faculty of Electrical Engineering, Delft University of Technology, the Netherlands, 2017;. In addition, he is a leading member of Cadence Academic Network on Dependability and Design-for-Testability.

Tutorial 6:

Title: "New Directions in Semiconductor Test and Validation "

Dr. C.P. Ravikumar


         Dr. C.P. Ravikumar is the Director of Talent Development at Texas Instruments, India. He is also an adjunct faculty of EE at IIT Madras. Before joining TI India in 2001, Ravikumar was a Professor of Electrical Engineering at IIT, Delhi (1991-2001). He also held a visiting position at the University of Southern California (1995-1996) and the position of Vice President (Training) at Controlnet India Pvt Ltd (2000-2001). He obtained his Ph.D. (Computer Engineering) from the University of Southern California (1991), M.E. in Computer Science with highest scores from Indian Institute of Science (1987) and B.E. in Electronics with a Gold Medal from Bangalore University (1983). He has published over 200 papers in leading International conferences and journals. He has 4 US patents in the area of VLSI Test. He founded the VLSI Design and Test Symposium (VDAT) and was the General Chair of this event from its inception in 1998 for 15 years. He is the author/editor/coauthor of over 15 books in areas of VLSI and has contributed several book chapters. He has served as an associate editor of IEEE Transactions on Circuits and Systems and has served on editorial board of the Journal of Electronic Testing – Theory and Applications and the Journal of Low Power Electronics. He has won the best paper award at IEEE International Conference on VLSI Design (2002) and VLSI Test Symposium (2005). He founded the Bangalore chapter of IEEE CAS society and was its honorary secretary for 15 years, and served as the honorary secretary of VSI for 6 years. He has served on the Execom of IEEE Bangalore Section (2017-2019). He is a Fellow of the INAE and a Senior Member of IEEE.