Panel Discussion - ITC India 2021
Title: "Has The Era Of Packetized Scan Architecture Arrived?"
Number of chip level pins at our disposal to be used for scan testing remains unchanged or is decreasing for the past several generations of chips. On the contrary, number of scan cells are growing very rapidly as the semiconductor technology advances to the next smaller node. Moreover, low power design styles and need of advanced fault models result into unmanageable scan test data volume. In response to these, test community has come up with a variety of potential solutions such as Streaming Scan Network, USB, PCIe, and Serdes based high speed scan interfaces. One of the notable developments to address this issue is IEEE 1149.10 Standard for High-Speed Test Access Port and On-Chip Distribution Architecture.
Come and listen to the industry experts debate on the existing architecture solutions, upcoming technologies and our preparedness for handling these as a DFx/Test community.