Panel Discussion - ITC India 2021

Title: "Has The Era Of Packetized Scan Architecture Arrived?"


          Number of chip level pins at our disposal to be used for scan testing remains unchanged or is decreasing for the past several generations of chips. On the contrary, number of scan cells are growing very rapidly as the semiconductor technology advances to the next smaller node. Moreover, low power design styles and need of advanced fault models result into unmanageable scan test data volume. In response to these, test community has come up with a variety of potential solutions such as Streaming Scan Network, USB, PCIe, and Serdes based high speed scan interfaces. One of the notable developments to address this issue is IEEE 1149.10 Standard for High-Speed Test Access Port and On-Chip Distribution Architecture.

       Come and listen to the industry experts debate on the existing architecture solutions, upcoming technologies and our preparedness for handling these as a DFx/Test community.

1. Punit Kishore


          Punit received his B. Tech. (EE) from IIT Kanpur in 2004. He is currently Engineer, Principal/Mgr at Qualcomm India Private Limited. He currently plays a design manager role to manage SOC end to end. Prior to design manager at Qualcomm, he has worked for Texas Instruments, NVIDIA and Intel. Punit has worked in different aspects of DFT like ATPG, diagnosis, mixed signal DFT, memory testing and repair, IO-DFT, CAD, Methodology development etc. He has worked extensively in defining automotive DFT architecture for ADAS and accelerator chips at Qualcomm. He holds 5 USPTO granted patents in the field of IO-DFT area. He has pioneered USB based testing of SOC.

2. Geir Eide


          Geir is the product management director for the Tessent Design-for-Test products at Siemens Digital Industries Software. As a 20 year-veteran of the IC DFT and test industry, Geir has worked with leading semiconductor companies and presented technical presentations and seminars on DFT, test, and yield learning throughout the world. Geir earned his MS in Electrical and Computer Engineering from the University of California at Santa Barbara, and his BS in microelectronics from the University of South-Eastern Norway.

3. Akshaye Sama


            Akshaye is a Master IC Engineer at Broadcom, where he is responsible for IC test for DSL line of products. He started his career at Philips Semiconductors designing digital IPs for TV and mobile SoCs, gaining expertise on most areas of digital IC design. Next was a deep dive into mixed signal circuits at Texas Instruments developing high speed SerDes for networking ASICs. During this time he developed an interest in testing for both digital and analog circuits. Since joining Broadcom in 2009, he has managed SoC DFT for multiple designs in Broadcom’s Mobile, Set Top Box and Broadband divisions. He holds a Bachelor of Engineering in Electronics and Communication from MANIT Bhopal(India) and Masters in VLSI Design from IIT Delhi(India).

4. Animesh Khare


             Animesh is currently Senior Engineering Manager at Nvidia Graphics, Bangalore, wherein he manages a team working on In-Field-Test. He has more than 15 years of experience spanning across DFX, architecture, logic design and verification. In his most recent role, he has architected High Speed Interface based Test Access Mechanism (TAM) for Nvidia SOC that can be used across Automatic Test Equipment (ATE), System Level Test (SLT) and In-System-Test (IST). He led end to end implementation of the TAM and ensured Day-0 silicon bring-up of the feature. His areas of expertise are In-System-Test ( software, architecture, design, verification) , High Speed I/O Test, User Defined Test and Scan Compression. His contribution in the field of research includes several US patents and publications. Prior to joining Nvidia, he was DFT lead at IBM System and Technology Group. He has M.Tech in Electronics and Electrical Communication Engineering from Indian Institute of Technology Kharagpur, India.

5. Denis Martin


          Denis received a B.Sc. degree and a M.Eng. degree both from McGill University, Montreal, Qc. He joined the Test Automation group at Synopsys, Inc. in the early ’90s. Since then he has been involved in all aspects of test automation, from scan synthesis and test access, to ATPG and diagnostics. Presently, he is a Synopsys Scientist and focuses on chip-level access technologies for manufacturing and in-system test.

Moderator: Kamlesh Pandey


        Kamlesh joined Qualcomm Bangalore in early 2021. He is currently leading ATPG vertical of Bangalore DFT group. Prior to joining Qualcomm, he has worked at Broadcom Bangalore for 17 years. At Broadcom he led a team working on DFT architecture, DFT flow development, DFT implementation on SOCs, ATE bringup and production support for Settop box and DOCSIS SOCs. Prior to joining Broadcom, he was DFT engineer at Cisco Systems for 4 years. His contribution in the field of research includes two US patents and invention of Broadcom in-house at-speed test architecture known as CTSA. He has received M.Tech. in Microelectronic and VLSI systems from Indian Institute of Technology Kanpur, in year 2001.