We are witnessing a rapid development of autonomous vehicles which are capable of executing all driving tasks under all driving conditions without a human driver. To accomplish this they employ advanced driver assistance systems which process, in real-time, large volume of data generated by multiple sensors and control actuators. Those systems not only have to deliver massive computing power but also need to be extremely reliable. With the growing number of very complex safety-critical components, one of the biggest challenges and stimuli of innovation is the requirement for extremely high quality and long-term reliability. In order to meet the performance demands, the more advanced technology nodes are adopted at an accelerated rate. The new technologies come with new more complex defects and reliability risks. In this talk we will review the key test innovations needed to meet the automotive requirements. Including, those to:
- meet the new quality of manufacturing and in-system test,
- satisfy the various constraints of in-system test (test time, memory, power, aging, cost),
- deal with arbitrary defect sensitivities.
Janusz Rajski, vice president of Engineering, Mentor, A Siemens Business, joined Mentor Graphics in 1995. During his tenure at Mentor he has built a strong R&D organization with focus on innovative Design for Test technologies and collaboration with leading semiconductor companies. Under his leadership the team has developed a number of revolutionary industry-first products: TestKompress, the first commercial test compression product, and Cell-Aware Test technology which provides unprecedented test quality and accuracy of diagnosis. Both are increasingly important for smaller technology nodes and automotive applications. He has published more than 240 IEEE research papers and is co-inventor of more than 100 US and corresponding number of international patents. His papers and patents have over 12,000 citations and won many prestigious awards, including two Donald Pederson best paper awards for papers published in the IEEE Transactions on CAD papers.
A Lifetime Fellow of the IEEE, he holds a Master of Science degree in electrical engineering from the Gdańsk University of Technology and a Ph.D. degree in electrical engineering as well as an honorary doctorate from the Poznań University of Technology. In 2003, he was awarded the prestigious title of “Professor of Science” by the President of Poland. In 2009 he received the Stephen Swerling Innovation Award from Mentor Graphics “for his breakthrough innovation, TestKompress, and his many contributions to revitalizing Mentor’s DFT business to its current position as #1 test business in EDA”. In 2018, Rajski received the Siemen’s Lifetime Achievement Award for his extensive contributions to DFT.
Today , many believe that DFT will continue to deliver the cost and quality required to meet the system requirements of the future. While , there has been significant improvements in structural testing, in my view, the improvements are linear. I believe we are at the dawn of a new age of DFT with sharply increasing criteria for quality and cost.
Today, traditional structural testing in advanced nodes is seeing exploding data set sizes and untested faults in advanced chips exploding past the size of chips a decade ago. To close some of the gaps in structural testing, fundamental changes may be needed. Options – Advanced fault models, testing via HSIO, increasing compression; System level testing, and others.
In this talk we will explore structural test, data size issues, untested/untestable faults, the potential world of test via HSIO, other facets of test in the world of advanced process nodes and need for machine learning in every engineers tool box. The talk will explore the issues faced with products having billions of transistors and how yield/test and structural testing in design, test, and product execution are all inter-related.
Come and explore the future of test , where improvements are needed, and where if we don’t adapt to the new reality – our extinction is a real possibility.
Michael Campbell is Senior Vice President of Engineering for QUALCOMM CDMA Technologies, responsible for QCT Product and Test Engineering, Test Automation and Failure Analysis. Mike joined QCT in 1996 as a Staff Engineer/Manager and since then Mike has led a diverse set of responsibility at Qualcomm, including, FA, Quality, Design Automation, Yield optimization, Product Engineering, Test Engineering, and Foundry semiconductor analysis.
At Qualcomm, Mike has helped bring up and drive the design office in Bangalore, the Design and test development center in Singapore and a development facility in Taiwan. In his current role, he is working to improve process bring up at our foundry partners, and 2nd source optimization. He is also working to optimize design processes in new process nodes to enable improved time to yield on Qualcomm’s products while enable faster time to market, at lower cost.
Prior to joining QUALCOMM, Mike was an engineer and manager at several semiconductor companies, including Mostek, INMOS and Honeywell. He holds a BSEE & CE from Clarkson University.
The semiconductor test industry has gone through a number of paradigm shifts over the past several decades in order to address continuously evolving test cost and quality challenges. Examples of these paradigm shifts include the move to scan-based testing in the 70s, the adoption of ATPG compression almost 20 years ago and the more recent proliferation of hierarchical test methodologies. Each of these new paradigms addressed a particular aspect of the test flow that became a critical limitation.
One limitation that is quickly becoming unsurmountable is the lack of communication bandwidth for cost-effectively transferring test data into the chip and extracting fail data out of it. The number of dedicated test pins and associated tester memory are not scaling with the continued rapid increase in test data volume. This talk introduces the new approach of leveraging existing functional high-speed interfaces like USB and PCI Express that are common on most chips to transfer test and result data in and out of the chip. In addition to providing necessary bandwidth and long-term scalability, this approach also enables seamless test portability as these high-speed functional interfaces can be accessed throughout the product life-cycle. This enables more extensive in-field testing and the ability to extract large amounts of test result data over time for new applications like adaptive test and predictive analytics for increased long-term reliability.
Steve Pateras is head of marketing for the test automation group within Synopsys. He has close to 30 years of experience in semiconductor test, both on the implementation side as well as in EDA. After beginning his career at IBM, Steve joined LogicVision as one of the company’s earliest employees. He held management positions both in engineering and marketing and was VP of Marketing when the company was acquired by Mentor Graphics in 2009. At Mentor, Steve drove the company’s initial move into key vertical test markets including 3DIC and automotive. Steve continues his passion for test innovation at Synopsys, expanding the company’s industry leading test products in new directions including advanced automotive functional safety, AI, 3DIC and adaptive test. Steve received his Ph.D. in Electrical Engineering from McGill University in Montreal, Canada.
Kaushik Narayanun is a Senior Director & Head of DFX Engineering at NVIDIA Corporation. He received a B.E.(Hons) in Electronics & Communication Engineering from University of Madras, an M.S. in Computer Engineering from University of California, Santa Cruz and an M.B.A.(Hons) from INSEAD, France. He has spent his career architecting and productizing DFX solutions for industry’s leading SOCs and GPUs. He has also helped solve challenging silicon manufacturing problems through multiple process node transitions including latest FinFET technologies. Mr. Narayanun is passionate about developing groundbreaking methodologies for system level test architectures and designs to deliver on quality and cost metrics. In the recent past, he has focused on reframing the needs of and leveraging the architectures in semiconductor test for solving imminent needs in Functional Safety, Resiliency and Reliability for new markets like Automotive, AI & Cloud.
Rohit Kapur is a Distinguished Engineer at Cadence in the area of Test Automation. Rohit is an IEEE Fellow and has a Ph.D. from the University of Texas at Austin specializing in IC Testing. Rohit has chaired the IEEE 1450.6 standard that defines the Core Test Language which is currently being used in the major EDA solutions. Rohit has served on the board of governors of Computer Society, he has chaired the standards activities for IEEE in the test area for over 10 years and currently serves on the board of IEEE Computer Magazine leading the publications in Computing Practices. Rohit is the author of a book and has over 100 publications and 40 patents in the area of IC test.