Tutorials:
Sunday, July 18, 2021 | |||
|---|---|---|---|
8:30 am – 9:30 am | REGISTRATIONS | ||
TRACKS | TRACK 1 Session Chair: Anurag Jain | TRACK 2 Session Chair: Shamitha Rao | TRACK 3 Session Chair: Kavitha Shankar |
HALL NAME | Zoom Meeting | Zoom Meeting | Zoom Meeting |
9:30 am – 11:00 am (15 mins. Break) 11:15 am – 12:45 pm | T1 : Identifying Good, Bad and Ugly chips through DFT : A Primer on VLSI Testing Abhishek Chaudhary(Texas Instruments India) | T2 : Advanced DFT and Security Technology for AI chips Lee Harrison, Peter Orlando,Jay jahangiri (Siemens EDA) | T3 : Addressing Test, Safety and Security for Connected Automotive IC’s Gajinder Panesar, Nilanjan Mukherjee, Raghav Mehta, Lee Harrison(Siemens EDA) Nir Sever, Gal Carmel (protean Tecs) |
12:45 pm – 1:45 pm | LUNCH BREAK | ||
1:45 pm – 3:15 pm (15 mins. Break) 3:30 pm – 5:00 pm | T4 : Testing Power and Clock Networks Prof. Shi-Yu Huang (Professor, Faculty of Electrical Engineering Department, National Tsing Hua University, Taiwan) | T5 : Device-Aware-Test for Emerging Memories: The means to win the war against unmodeled faults Said Hamdioui (Delft Universitty of Technology) | T6 : New Directions in Semiconductor Test and Validation Dr. C P Ravikumar (Texas Instruments India) |
Conference:
Monday, July 19, 2021 | ||||
|---|---|---|---|---|
8:00am-9:00am
| REGISTRATIONS | |||
SESSIONS | Morning Keynotes | |||
Meeting Links | Zoom Meeting | |||
9:00am – 9:10am | Inauguration/Welcome | Navin Bishnoi, General Chair, ITC India 2021
| |||
9:10am – 9:50am | Keynote 1: “The Critical Role of Analytics from Silicon to Systems” | Amit Sanghani, Sr. Vice President – Hardware Analytics and Test, Synopsys | |||
9:50am – 10:30am | Keynote 2: “Test Optimization for High-Performance, Advanced Technology SOCs” | Phil Nigh, Distinguished Technical Staff Member, ASIC Product Division, Broadcom | |||
10:30am – 11:00am | TEA/COFFEE BREAK SESSION
| |||
SESSIONS | Session 1 – High Quality Memory Test & Advanced Fault models Session Chair: Venkata Rangam Totakura | Session 2 – Functional Safety & Hardware Security Session Chair : Prof Indranil Sen Gupta | ||
HALL NAME | Zoom Meeting | Zoom Meeting | ||
11:00am-12:30pm
| 1.1 Addressing High Speed Memory Interface Test Quality Gaps in Shared Bus Architecture 1.2 Core Test Language based High Quality Memory Testing and Repair Methodology 1.3 Targeting Zero DPPM through Adoption of Advanced Fault Models and Unique Silicon Fall-out Analysis | 2.1 Parallel Field Test Architecture for Boot-ROMs in Safety-Critical SoCs 2.2 Comprehensive In-field Memory Self-Test and ECC Self Checker –Minimal Hardware Solution for FuSa 2.3 Side-channel Analysis for Hardware Trojan Detection using Machine Learning. | ||
12:30pm-1:30pm
| LUNCH BREAK | |||
SESSIONS
| Test Reality Check (TRC) Track Session Chair | Kavitha Shankar | Academia Research Track (ART) Session Chair | Ankush Srivastava | ||
HALL NAME | Zoom Meeting | Zoom Meeting | ||
1:30pm-3:00pm
| TRC1.1 In Silicon Soft Error Injection DFT Technique for RAM REPAIR validation TRC1.2 Yield Improvement techniques in Slow-Slow Devices during High Volume Manufacturing TRC1.3 ScanDump made Easy! – An IJTAG based approach TRC 1.4 Innovative ways to address FPGA prototyping challenges of DFT IP | ART 1.1 Adapting AI into Low Power Testing ART 1.2 Logic Locking: The Future of Secure Hardware Design (Invited) ART 1.3 Understanding Test Escapes from Classical Stuck-at and TDF Tests (invited) | ||
3:00pm-3:30pm
| TEA/COFFEE BREAK SESSION
| |||
SESSIONS
| Poster Session 1 Session Chair | Kavitha Shankar and Vineet Srivastava | Poster Session 2 Session Chair | Kamlesh Pandey and Amanulla Khan | ||
HALL NAME | Zoom Meeting | Zoom Meeting | ||
3:30pm-4:30pm
| Poster 1.1 Left Shift & Correct by Construction DFT-RTL Design Poster 1.3 DFT Strategy for Safety devices with Aging Detection Requirements Poster 1.4 Memory interface faults and the PPM requirements – The indecisive ram-sequential test Poster 1.5 Spyglass Netlist level Check – Methodology on Low Power Mixed Signal Design Poster 1.6 A Survey of Embedded Memory Testing | Poster 2.1 Automating silicon ATE bringup Poster 2.2 Novel Approach for DFT Test time Reduction Poster 2.3 Effective defect screening techniques: The outright need of high-quality test Poster 2.4 A Novel Approach to minimize Coverage Drop between Pre-PnR to Post-PnR Netlist in SoC VLSI Design Poster 2.5 Configurable Scan Wrapper Architecture Poster 2.6 High throughput Multiple Device Diagnostics for Hierarchical Test Designs | ||
HALL NAME | Zoom Meeting | |||
4:30pm-5:00pm
| Invited 1: Design Closure and Test Challenges in Addressing Automotive Quality with High-speed IO Interfaces Lei Wu, Rajagopal K.A, Devanathan Varadarajan Texas Instruments | |||
5:00pm-5:05pm | Day 1 – Closing / Wrap-up | |||
Tuesday, July 20, 2021 | ||||
|---|---|---|---|---|
8:00am-9:00am
| REGISTRATIONS | |||
Meeting Link
| Zoom Meeting | |||
9:00am-9:10am
| Welcome | Navin Bishnoi, General Chair, ITC India 2021
| |||
9:10am-9:50am
| Keynote 3: “Tackling the test challenges of the chiplet revolution” | Jeff Rearick, Senior Fellow, Advanced Micro Devices
| |||
9:50am – 10:30am | Keynote 4: “Elevating 2D Design and Test to 3D” | Vivek Chickermane, Distinguished Engineer, Cadence
| |||
10:30am – 11:00am | TEA/COFFEE BREAK SESSION
| |||
SESSIONS | Invited Talk & Panel Discussion Session Chair | Kamlesh Pandey | |||
Meeting Link
| Zoom Meeting | |||
11:00am-11:30am
| Invited 2: “IEEE P2851 Standards on Functional Safety Interoperability” | Jyotika Athavale, NVIDIA
| |||
11:30am-12:30pm
| Panel Topic: Has the era of packetized scan architecture arrived? Moderator: Kamlesh Pandey (Qualcomm, Bangalore) | |||
12:30pm-1:30pm
| LUNCH BREAK | |||
SESSIONS
| Session 3 – Best Practices in Accelerated Pre-Silicon Verification, Analog & Stress Testing Session Chair: Prof Dr. Jaya Gowri | Session 4 – Power Aware Test Prediction & Optimization Session Chair : Srinivasan Chandrasekaran | ||
Meeting Link | Zoom Meeting | Zoom Meeting | ||
1:30pm-3:30pm
| 3.1 Accelerating GLS Simulation closure in DFT with Emulator Hardware 3.2 Method and Apparatus for Bug Free Rapid Silicon Bringup 3.3 A Novel Method to measure PLL Bandwidth in a 5G RF transceiver 3.4 An Efficient Test Architecture for Concurrent Over Voltage Stress Testing (OVST) of Logic and Memory | 4.1 A Fast Robust Operation Mode invariant Frame-work for IR drop Prediction 4.2 An Improved Test Pattern Reordering Framework Targeting Test Power Reduction 4.3 16x Multisite, High Current and High Power density Test Solution for Power Protection Device 4.4 Runtime Test Solution for Adaptive Power Optimization of Edge AI devices | ||
3:30pm-4:00pm
| TEA/COFFEE BREAK SESSION
| |||
SESSIONS
| Closing Ceremony Session Chair | Navin Bishnoi | |||
Meeting Link | Zoom Meeting | |||
4:00pm-4:30pm
| Keynote 5: “Design-for-Testability: Setting the Cornerstone for Successful Manufacturing” | John Carulli, Director, PostFab Test Development Center, GLOBALFOUNDRIES
| |||
4:30pm-4:40pm
| Conference Closing/Wrap-up
| |||