Important Dates
Please note: We require the authors to follow this paper template: https://www.ieee.org/content/dam/ieee-org/ieee/web/org/conferences/Conference-template-A4.doc
The Call For Submission for Academia Research Track 2021 is live!
Authors are invited to submit truly innovative and “out-of-the-box” ideas that may not yet have been fully developed for presentation at reviewed conferences to address design and test related challenges. The idea of is to manifest and publish creative research ideas from students and young academicians. The key objective of this track, for the first time planned to be held with the International Test Conference, is to provide a dedicated informal forum for vigorous creative discussion and debate of this area from researchers of various academic institutes. Please follow the submission guidelines as mentioned below.
Additional Benefits: Registration fee waiver will be provided through fellowship available at http://bit.ly/ITCIndia2021_Fellowship
Note: For detailed information about the submission process, requirements and deadlines, the selection process and any other questions regarding the program itself or contact information, please consult the ITC India web site at http://www.itctestweekindia.org or email the program chair at [email protected]
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ITC India invites submissions from students, young researchers and academicians to publish their novel ideas on the latest advances in test, verification, diagnosis of ICs, boards and systems.
3D/2.5D Test
RF, mm-Wave and THz testing
Adaptive Test in Practice
ATE/Probe Card Design
Advances in Boundary Scan
Bring Up
Data Driven Methods
Data Exchange and Infrastructure
Defect-Oriented Testing
DFM and Test Diagnosis
Economics of Test
End-to-End Data Analysis
Embedded BIST & DFT
Emerging Defect Mechanisms
Hardware Security and Trust
IoT Testing
Known-Good-Die testing
Memory Test and Repair
MEMS Testing
Mixed-Signal and Analog Test
New Technologies and Test
On-Chip Test Compression
Online Test
Pre- and Post- Silicon Validation
Power Issues in Test
Protocol-aware Test
Reliability and Resilience
Scan Based Test
SoC/SiP/NoC Test
Silicon Debug
Jitter, High-Speed I/O and RF Test
Simulation and Test
System Test (Applications)
System Test (Hardware/Software)
Test-to-Design Feedback
Test Escape Analysis
Test Flow Optimizations
Test Generation and Validation
Test Resource Partitioning
Test Standards
Test Time Analysis and Reduction
Testing High Speed Optics/Photonics
Timing Test
Yield Analysis and Optimization