Navin Bishnoi

Navin is Director, ASIC India Design Center at GLOBALFOUNDRIES and leads Customer ASIC Design as well as the definition & development of Methodology. He is responsible to drive the Global strategy and roadmap for tools, methodology, and architecture in the area of DFT/Test, Automotive and Low Power. Prior to this, he was with IBM EDA group, leading the development of tools and methodology for DFT, Physical Implementation, and Sign-off flows. He has worked with Freescale, Cadence, and TI for automotive, consumer and custom ASIC designs. He had received his Bachelor’s degree in Electronics and Communication from NIT Surathkal in 1998. He has extensive experience in the field of ASIC designs and required tools/methodology and has been an active member in EDA standards, conferences and review committees. He has been in steering/conference committee for VLSID itc_archives/2017, Automotive and Reliability Test Workshop @ ITC 2016/itc_archives/2017, ITC India itc_archives/2017.

Prasad Mantri

Prasad Mantri is Principal Engineer at the Microelectronics group at Oracle Systems group. He is involved in Design for Test, Microprocessor Test strategy, Test data volume and test time enhancement, Silicon yield analysis and yield debug, System failure analysis and debug as well as reliability and system product quality. He has worked at Sun Microsystem and Oracle Corporation for the past 13 years working on all their microprocessor designs. Before that, he has worked at Synopsys Inc, SGI, Micron and Silicon access. He has multiple papers and patents in logic and memory test. He has contributed to International Test Conference as a reviewer. He was on the organizing committee of ATE Vision 2020 conference. He has contributed to the ITRS Design and Test roadmap for multiple years as well as presented at the 3D IC design and test workshop organized by Sematec. He is a senior member of the IEEE and has contributed as a volunteer and is working on white papers on IEEE Internet Initiative. He has M Tech from IIT Madras

Krishna Rajan

Krishna is Director of Hardware Engineering at Nvidia Graphics, Bangalore, India, where he leads a team to deliver DFT solutions for all Nvidia chips. Responsibility spans across all aspects of DFT – architecture, methodology, flow development, implementation, verification, manufacturing test development, silicon bring up and diagnosis. Prior to Nvidia, he was with Sun Microsystems, California, USA where he worked on ASIC and microprocessor DFT. He has co-authored several papers in leading test conferences and a co-inventor of 5 US patents in the area of testing. He has a BE degree in ECE from SJCE, Mysore, India, M.E. in Applied Electronics from PSG College of Technology, Coimbatore, India, and Ph.D. in Electrical Engineering from Illinois Institute of Technology, Chicago, USA.

Prakash Narayanan

Prakash Narayanan is a Sr.Technical Lead, Member Group Technical Staff at Texas Instruments India Pvt. Ltd. He is responsible for leading the DFT efforts for several projects at TI ranging from wireless microcontroller SOCs to the most recent mmWave Radar SOCs being developed at TI. He has several granted patents in logic and memory test with several more filed. He has co-authored conference papers at ITC, VTS, DATE, and IOLTS apart from many papers at EDA vendor conferences and TI internal over the years.

Venkata Rangam Totakura

Venkata is Design Engineering Director at Cypress Semiconductor Technologies. He is responsible for Chip Integration Center (CIC), implements Synthesis to GDS flow activities for various ASIC products of different Business Units such as Memory, Programmable SoC, Data Communication, and Automotive. He is New Product Development team member and responsible to develop and drive common ASIC implementation methodology across Cypress. He is DFT CoE (Centre of Excellence) quorum member and DFT-QA review board member at Cypress. He has Masters degree in VLSI CAD. He has 16 years of work experience in VLSI industry, worked for Mentor Graphics, Infineon and NXP organizations intensively into DFT domain. He authored/co-authored 10 papers in DFT and low power domains.He has an extensive experience in the field of ASIC design, implementation and successfully completed multiple Tapeouts in various technology nodes. He has been an active member in EDA standards, conferences and review committees.

Jais Abraham

Jais Abraham is Director of Design Engineering at Qualcomm India Pvt. Ltd., where he focuses on the Design-For- Test methodology for mobile SoCs. After graduating in Electronics Engineering from IIT- Chennai, he worked at Texas Instruments, AMD and most recently at Intel, looking into the DFT of various classes of products ranging from extremely cost-sensitive products to high speed processors and also products with stringent quality requirements. Jais has co-authored multiple technical papers in various conferences and is an co-inventor of 6 patents.

Srijesh Parambath

Srijesh Parambath has been associated with Mentor since 2008 and is managing the DFT India Technical team out of Bangalore. Prior to Mentor, he was with CoreEL Technologies owning functional responsibilities of Design, Applications and Architecture definition in the areas of VLSI & Hardware Engineering. A technologist with 15 years of experience in EDA, ASIC & System design domains, Srijesh has a Bachelor degree in Electronics & Communications from Bangalore University.

Veerappan V

Veerappan brings Rich experience of more than 33 years. He was associated with Sterling Electronics a pioneer in the Indian Electronics Industry following which he become a Territory Manager of DCM Data Products. He oversaw national level sales and customer supports operations with Wipro Technologies before moving on to Motorola as GM-Operations in charges of MIS, Facilities, HR, Admin, PR, Systems and Commercial. Before joining Tessolve, Veerappan was associated with BPL Telecom as their Head of Operations & Business Development.

Krishnan Sreenivasan

Krishnan C.S. has more than two decades of experience in administrative finance and operations management domain. He is head of administration and operations at AB Innovative. In his previous role he served as head of operations at Tessolve Semiconductors for about 9 years.

Thryambak Chandilya

Thryambak Chandilya is the Director of the Test Solutions Group at Synopsys, India. He has 18 years of experience in Design-for-Test and prior to his current role, he has been at Mentor Graphics (leading field applications and customer support teams) and Altera (designing DFT structures to test the FPGA fabric). 
In his current role at Synopsys, his team is responsible for working with customers to develop new DFT flows and methodologies across a wide variety of designs and applications. 
He has a Masters degree in Electrical and Electronics Engineering from the University of Florida in Gainesville.

Veeresh Shetty

Veeresh is the Senior Marketing Manager at Mentor and is responsible for driving the marketing activities including brand affinity and loyalty amongst the customer base. He has over 18 years of Industry leadership experience with strong competency in branding, marketing, marketing communication and digital marketing. He charters Mentor’s growth strategy and creates opportunities in existing and potential markets in the region.  Veeresh is responsible for creating integrated marketing programs to drive customer connect and also enhance the brand equity of Mentor. Veeresh holds an MBA and a Post Graduate certification in digital marketing from MICA. Post his masters, he has finished his higher studies from Wharton Business School, US.

Samuel

Samuel is the Operations Manager at Intel with over 15 years’ experience in Operations & Project Management at various levels of the organization. He is responsible of managing operations including people systems, process, risks & controls and infrastructure. He holds an MBA and is a certified PMP (Project Management Professional) & Lean Six Sigma certified. He has been part of many International conference steering committees like International VLSI & Embedded Systems conference, DVCon 2018 India as the Conference & Exhibition chair. He has strong expertise in planning & managing large International conferences & symposiums.

Neelakandan Eswaran

Neelakandan Eswaran is presently associated with Altran Technologies as a Technical Unit Manager and leads ATE test and product engineering business unit. He is involved in managing the projects, resource allocation, SOW, milestone definition, and the team. His responsibility is to provide end to end support for clients in ASIC test lab installation and maintenance, ATE board design, off-shore silicon debug, new product bring up debug, production release, yield enhancement, test time reduction, DPPM reduction and sustaining support for devices till EOL. 
Prior to Altran, he was with Tessolve as a Senior Test Lead and worked with various key customers like Texas Instruments, Qualcomm, Maxim, Intersil, and NI in different geographies. He has expertise in defining test solutions for mixed signal IC’s, and hi-speed digital SOC’s. He has graduated from Anna University as an Electronics and Communication Engineer and holds Master of Business Administration in Project Management from Sikkim Manipal University. He is also pursuing his Ph.D from Annamalai University in Human Resource Management.

Sameer Chillarige

Sameer is Sr. Software Engineering Manager in Modus DFT Software Solution R&D group at Cadence Design Systems and heads the Diagnostics R&D Team. He is responsible for defining the road map of Diagnostics product and drives the development of latest features working closely with customers. In his 14 years of work, he and his team are responsible for development of numerous new functions in Diagnostics product in the areas of logic and scan chain diagnostics, physically-aware volume diagnosis. He has co-authored multiple technical papers in various external and Cadence internal conferences and is a co-inventor of 6 patents with several more filed. He has a Bachelor’s degree in Electrical and Electronics from BITS, Pilani.

Nagesh Tamarapalli

Nagesh is an AMD Fellow with AMD India Design Center in Bangalore, India, where he leads a team engaged in high-quality manufacturing test for next generation microprocessors. The team’s mandate spans the entire life cycle of DFT including architecture, implementation, verification, manufacturing test development, silicon bring up and diagnosis. Prior to AMD, he was with Mentor Graphics DFT group where he worked on logic BIST, test compression, and diagnosis tools. He has published several papers in leading test conferences and a paper he co-authored at International Test Conference 1999 on logic BIST has been recognized with “Honorable Mention Award”. He is a co-inventor of 18 US patents in the area of testing. He has delivered DFT seminars at several venues including multiple VLSI Design Conference, ISQED 2007 and DAC 2008. He holds B.Tech. In ECE from REC Warangal, M.Tech. in Electrical Engineering from Indian Institute of Technology, Kharagpur, India, and Ph.D. in Electrical Engineering from McGill University, Montreal, Canada.

Animesh Khare

Animesh is currently Senior Engineering Manager at Nvidia Graphics, Bangalore, wherein he leads a team working on DFT methodology. He has over 13 years of experience spanning across all aspects of DFT. His contribution in the field of research includes several US patents and publications. His areas of expertise are In-System-Test, Cell Aware Test, Scan Compression and High Speed I/O Test. Prior to joining Nvidia, he was DFT lead at IBM System and Technology Group. He has M.Tech in Electronics and Electrical Communication Engineering from Indian Institute of Technology Kharagpur, India.

Sivanantham S

Sivanantham is working as an Associate Professor in the School of Electronics Engineering, VIT University, Vellore, India. He worked as an Assistant Director for International Relations Office during 2014-15. He served as a Leader for VLSI and Embedded System Division at VIT University during 20072009. Previously he was associated with J.J. College of Engineering and Technology, Trichirappalli, India and Bannari Amman Institute of Technology, Satyamangalam, India as a faculty in the Department of Electronics and Communication Engineering. His area of research interest includes the design for testability, reconfigurable architectures, and low power VLSI design. He is the Senior Member of IEEE and member of IEICE, VLSI Society of India (VSI) and Indian Society for Technical Education (ISTE).

Vineet Srivastava

Vineet is Engineering Manager at Intel. He is responsible for implementing Best in Class DFT solutions for IOTG products. Prior to this, he was with PMC-Sierra, leading the worldwide DFT team across Business Units. He was instrumental in setting-up DFT-CoE at PMC-Sierra, Bangalore. He has worked with Freescale, Infineon and TI for automotive, networking & Wireless products. He received his Bachelor’s degree in Electronics from Z.H. College of Engineering & Technology, A.M.U. Aligarh in 2000. He is passionate about Day-1 Silicon Bring-up & spreading DFT/Test awareness in engineering colleges. He had delivered lecture & conducted DFT workshop in Thapar Institute of Engineering & Technology. He has extensive experience in the field of DFT & Test implementation/tools/methodology and presented couple of papers in different VLSI conferences.   

Prof Virendra Singh

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Shridhar Bendi

Will Be Update Soon!