Tutorials

Sunday, July 22, 2018
8:30am-9:30am Registrations
Track 1 Track 2 Track 3
9:30 am - 11:00 am
(15 mins. Break)
11:15 am - 12:45 pm		 T1: Machine Learning in Test
Dr.Yu Huang, Gaurav Veda; Mentor Graphics 		T2: Automotive Reliability & Test Strategies
Dr. Yervant Zorian (Synopsys), Riccardo Mariani (Intel); 		T3: Test Access Mechanism (TAM) for Advanced SoCs
Punit kishore (Qualcomm), Jais Abraham (Qualcomm), Shamitha Rao (Mentor), Srijesh Parambath (Mentor)
12:45pm-1:45pm Lunch Break
1:45 pm - 3:15 pm
(15 mins. Break)
3:30 pm - 5:00 pm		 T4: Are System Level Tests Unavoidable for High End Processors?
Dr. Adit D. Singh, Auburn University 		T5: Recent Trends in Modelling and simulation of Defects in Analog Circuits and their Applications
Vijay Kumar Sankaran (Cadence), Lakshmanan Balasubramanian (Texas Instruments), Nadeem Tehsildar (Texas Instruments) 		T6: Logic Encryption: A Design-for-Security Trust Methodology for Digital Integrated Circuits
Prof. Santanu Chattopadhyay, Rajit Karmakar; IIT-Kharagpur

Conference

Monday, July 23, 2018
8:00am-9:30am Registrations
9:30am-9:50am Inauguration/Welcome
9:50am-10:20am Keynote 1: "Infrastructure IP for Today’s Automotive SOCs", Yervant Zorian, Synopsys
10:20am-10:50am Keynote 2: "Testing in Always on Era", P Raja Manickam, Tessolve
10:50am-11:15am Tea/Coffee Break
11:15am-12:45pm Session 1 - Memory Test & Repair Session 2 - Debug & Diagnosis
12:45pm-1:45pm Lunch Break
1:45pm-2:15pm Special Talk on "5G mm Wave Future Testing Methodology at ATE level", Tan Kheng How, Regional Application Consultant, Advantest Exhibits / Booth
2:15pm-3:15pm Demo
3:15pm-3:30pm Tea/Coffee Break
3:30pm-5:00pm Session 3 - Automotive Test Session 4 - Mixed Signal & Analog Test
5:30pm-6:30pm Panel Discussion: "Fault tolerance or fault intolerance: what's the way forward?"
6:30pm-9:30pm Dinner with Cultural Evening
Tuesday, July 24, 2018
8:30am-9:30am Registrations
9:30am-9:40am Welcome / Day 1 Summary
9:40am-9:55am Special Talk on "Test Technology Technical Council (TTTC)", Yervant Zorian, TTTC Chair
9:55am-10:25am Keynote 3: "Self-Driving Cars – how they are pushing the boundaries of IC Testing.", Nilanjan Mukherjee, Mentor Graphics
10:25am-10:55am Keynote 4: "Directions in Advanced Packaging Technology", Ravi Mahajan, Intel
10:55am-11:15am Tea/Coffee Break
11:15am-12:45pm Session 5 - DFT Architecture Session 6 - Test Challenges
12:45pm-1:45pm Lunch Break
1:45pm-2:45pm Demos Exhibits / Booth
2:45pm-3:10pm Tea/Coffee Break
3:10pm-4:40pm Session 7 - Test Potpourri Session 8 - Standards
5:00pm-5:30pm Awards Function / Closing Ceremony

Paper Session

July 23 - Monday 11:15am-12:45pm
Session1: Memory Test & Repair
Session Chair: Animesh Khare
1-1. Improved RAM Sequential Tests for SoCs with Complex Memory Architectures
Wilson Pradeep and Prakash Narayanan
1-2. Automated Identification of Embedded Physical Memories using Shared Test Bus Access in IP Cores
Puneet Arora, Norman Card, Steven Gregor, Navneet Kaushik and Prashant Kulkarni.
1-3. Catalyst & Optimized Vector generation Methodologies for BIST and Multi-Core Repair Validation
Boopala Krishnan, Sumit Emekar, Prasanna Ramanujam and Subrahmanya M.
July 23 - Monday 11:15am-12:45pm
Session2: Debug & Diagnosis
Session Chair: Arvind Jain
2-1. High Accuracy, Robust Multiple Defect Diagnosis Scheme
Bharath Nandakumar, Anil Malik, Sameer Chillarige, Anshul Kumar, Joe Swenton and Atul Chhabra.
2-2. Pylon: Towards An Integrated Customizable Volume Diagnosis Infrastructure (Invited)
Atul Chittora, GlobalFoundries
2-3. High Throughput Multiple Device Diagnosis System (Invited)
Sameer Chillarige, Anil Malik, Joe Swenton, Krishna Chakravadhanula
July 23 - Monday 3:30pm-5:00pm
Session3: Automotive Test
Session Chair: Kamlesh Pandey
3-1. Enhancing Automotive Self-Test with Embedded Distributed Programming
Carl Wisnesky II and Patrick Gallagher.
3-2. Breaking Test Coverage and Test Cost Barrier for Safety Critical Automotive Designs Targeting Zero DPPM
Wilson Pradeep, Aravinda Acharya and Nikita Naresh.
3-3. DFT strategy in automotive devices with low cost testing requirements
V Srinivasan, Sabyasachi Das, Manish Sharma and Tripti Gupta.
July 23 - Monday 3:30pm-5:00pm
Session4: Mixed Signal & Analog Test
Session Chair: Rajesh Khurana
4-1. Modeling and Simulation of Defects in Analog Circuits: Fault Modeling, Simulation and Coverage Calculation
Vijay Kumar, Lakshmanan Balasubramanian, Victor Zhuk and Nadeem Husain Tehsildar.
4-2. RF Senstivity test(7.5GHz) in non RF configuration using on board components
Sivapavan Anala, Purnachandra N, Jagadish Chandrasekaran and Srinivasan Chandrasekaran.
4-3. Challenges in analog loopback testing for RF transceivers
Nagarajan Viswanathan, Vidhya Lakshmi M, Nithin Gopinath, Shuhood Mohamed and Subbarao Nalluri.
July 24 - Tuesday 11:15am-12:45 pm
Session5: DFT Architecture
Session Chair: Pramod Notiyath
5-1. Testability of High-speed On-Chip Interconnect on ATE
Vishwajit Reddy, Amanulla Khan, Pradeep Bhat, Vinod Pagalone, Punj Pokharel and Suhas Satheesh.
5-2. A Novel Test Wrapper Architecture Design for Scan as well as Functional Test
Khushboo Agarwal and Ahmet Tokuz.
5-3. IP Design for Test Considerations for an Automotive End Application
Teresa McLaurin and Ke Peng.
July 24 - Tuesday 11:15am-12:45 pm
Session6: Test Challenges
Session Chair: Hasan Sheikh
6-1. HBM operation and testing challenges
Narayanaswamy Muniyappa, Arun Kumar Chockalingam and Neelakandan Eswaran.
6-2. Test and Characterization of High Speed I/Os
Harsh Baghel, Vinod Kolluru and Krishna Rajan.
6-3. Test of Low Cost Microcontrollers: Challenges and Solutions (Invited)
Malav Shah, Texas Instruments
July 24 - Tuesday 3:10pm-4:40pm
Session7: Test Potpourri
Session Chair: Kanwaldeep Sobti
7-1. Post Fabrication Fix for RF DIB Design Problems
Jagadish Chandrasekaran, Kandhan Rajakumar, Srinivasan Chandrasekaran and Gowrishankar Ilankumaran.
7-2. Hardware Trojan Prevention and Detection Used in Integrated Circuits
Jayanthi Daniel and Joshi Hrushikesh.
7-3. Power Efficient Circuit implementation for High Speed Digital Design
Renuka Nagapurkar.
July 24 - Tuesday 3:10pm-4:40pm
Session8: Standards
Session Chair: Vikram Somaiya
8-1. Practical aspects of a IEEE 1687 (Invited)
Rajesh Khurana, Cadence Design Systems; Sreekanth Pai, Global Foundries
8.2 Meeting ISO 26262 requirements for analog and digital ICs
Stephen Sunter, Mentor Graphics

Demo Session

Monday 23 Jul   1.45pm – 3.15pm
Demo Registration Link: https://docs.google.com/forms/d/e/1FAIpQLSepkwe8wFQNCuJ_IdtDJG863-dLz3V8h-oskxxn6j1HFEK-LA/viewform?c=0&w=1
A Game Changer: Evolutionary system to highly efficient design evaluation
"Very often the setup and analysis report of an evaluation task outrun the measurement time itself. This new low cost measurement system allows engineers to quickly build their own measurement environment without tediously combining several standalone instruments. The software GUI is extremely intuitive, enabling engineers to create device focused measurement setups in a very fast and simple manner. Automatic report functions dramatically improves the efficiency of deskwork."
Tuesday 24 Jul   3.30pm – 5.00pm
Demo Registration Link: https://docs.google.com/forms/d/e/1FAIpQLSepkwe8wFQNCuJ_IdtDJG863-dLz3V8h-oskxxn6j1HFEK-LA/viewform?c=0&w=1
A paradigm shift : CloudTestingTM Service for Skill development & Design
"CloudTestingTM Service leverages recent advances in cloud computing that have transformed the concept of ownership from physical possession of an asset to a licensing agreement, with the asset itself residing in the cloud. Applying this paradigm to semiconductor test, a new business model was developed that expands customer access to testers by delivering test IP directly to their personal computers, making it ideal for any skill development & design needs of academia, research & design company."