Call For Tutorials


Authors are invited to submit high quality, practical and industry best practices.


Tutorial title and Tutorial program with a list of topics covered, a short description of each topic and the approximate time devoted to each topic (about 2000 words)
The targeted audience and prerequisites (about 50 words)
Tutorial duration should be 3:00 hours
Name, affiliation and contact details of the co-ordinating presenter and all other co-presenters.
Proposals will undergo a panel review process.
All presenters listed in the tutorial proposal must be available for tutorial presentation.
Consent should be obtained from all the presenters and all organizations involved in presenting the material before making the tutorial proposal.
Accepted tutorial abstracts will be published in conference proceedings.


Proposal Submission deadline: April 15, 2018
Author Notification : May 18, 2018
Final Manuscript Due : Jun 15, 2018

ITC India invites submissions on the latest advances in test, validation and diagnosis of ICs, boards and systems.

Topics of interest include (not limited to):

3D/2.5D Test

Adaptive Test in Practice

ATE/Probe Card Design

Advances in Boundary Scan Up

Data Driven Methods

Data Exchange and Infrastructure

Defect-Oriented Testing

DFM and Test Diagnosis

Economics of Test

End-to- End Data Analysis

Embedded BIST & DFT

Emerging Defect Mechanisms

Hardware Security and Trust

IoT Testing

Jitter, High-Speed I/O and RF Test

Known-Good- Die testing

Memory Test and Repair

MEMS Testing

Mixed-Signal and Analog Test

New Technologies and Test

On-Chip Test Compression

Online Test


Pre & Post- Silicon Validation

Power Issues in Test

Protocol-aware Test

Reliability and Resilience

Scan Based Test

Security issues in TEST

SoC/SiP/NoC Test

Silicon Debug

Simulation and Test

System Test (Applications)

System Test (Hardware/Software)

Test-to- Design Feedback

Test Escape Analysis

Test Flow Optimizations

Test Generation and Validation

Test Resource Partitioning

Test Standards

Test Time Analysis and Reduction

Testing High Speed

Timing Test

Yield Analysis and Optimization

Please send your submissions to ( [email protected])

Proposals are to be submitted only in pdf form, following above given guidelines. Authors of accepted Tutorials are responsible for preparing the final manuscripts in time, to be included in the electronic proceedings.