Keynote #1

Srini Maddali

Vice-President (Technology), Qualcomm

Title: Mobile Evolution - Challenges for Test

Abstract: The rapid proliferation of mobile technologies in the last few years and the projected growth of IoT devices in the coming years has thrown up new challenges for the semiconductor design industry. While increased performance & functionality have driven the need for more integration, there has been a constant pressure on the production costs to maintain the profitability of these products. New process technology nodes are being adopted almost on a yearly cadence to keep pace with these seemingly conflicting product requirements. Test technology is a key enabler in this push for product scaling by playing an important role in yield learning and the quality of shipped devices. This keynote will highlight the trends in the mobile and IoT semiconductor markets, the challenges that it poses for test and calls for solutions to make the right tradeoffs in the test methodologies.

Biodata: Srini Maddali is Vice President , Technology at Qualcomm India Design Center and leads the Mobile SoC development Engineering teams. His current areas of focus is Low-Power, High-Performance SoC design and enabling rapid ramp to volume of these designs. Srini has been in the VLSI industry for the past 22 years, 14 of them with Qualcomm and his experience spans across Circuit Design, Memory Cell Design, High Speed Memory/System Interface Designs and Architecture. Srini has a Masters in Engineering Physics from REC Warangal.

Keynote #2

Gianluca Colli

Vice President & GM, Consumer Solutions Division – Image Sensor Group, ON Semiconductor

Title: Next Generation CMOS Image Sensor (CIS) : Test and Reliability challenges for new emerging applications

Abstract: New trends in technologies are driving a growth in CIS applications for Virtual Reality/Augmented Reality (AR/VR), Scanning, Drone and Autonomous Driving. These new applications are requiring newer and better CIS sensors that create challenges in the fields of Test and Verification. This talk explains details about these new markets requirements and what we are doing to improve test and reliability of CIS devices.

Biodata: Gianluca Colli is currently Vice President, Consumer Solution Division within the Image Sensor Group, ON Semiconductor where he is responsible for definition, design and manufacturability of CIS products. Prior to that, Gianluca served as the general manager for the Mobile Device Power business unit for Texas Instruments in Santa Clara, California where he managed a $400 million business and a team of 200 where his most recent focus has been in the areas of power management solutions for mobile applications (smartphones, tablets, laptops) and automotive (ADAS and infotainment). Prior to that, he held multiple senior business management positions and high profile engineering management roles. Through the course of his career, he has been responsible for design, test, product engineering and application across several design centers worldwide in both Texas Instruments and National Semiconductor. Born in Italy, Gianluca moved to Silicon Valley in 1996 as analog design engineer working for STMicroelectronics. He received a Bachelor of Science in electrical engineering and Master of Science in electrical engineering from University of Pavia, Italy, and holds 11 U.S. patents and authored several technical papers on analog design techniques.

Keynote #3

Ron Press

Technical Marketing Director – Silicon Test Solutions group, Mentor Graphics

Title: Why You Want Test to Become an Afterthought, Again

Abstract: Nobody in the electronics test industry actually wants test to be an afterthought. When test has been an afterthought and technology advances and discontinuities occur, it has been very painful and expensive. In response, the test industry has come up with new methodologies, infrastructures and automation. These result in the test activities shifting earlier and with more automation in the design flow to the point they become almost transparent. Test professionals are able to work at a different level of abstraction. Scan technology shifted the work of test practitioners such that they can focus on pattern generation operations and not need to know the specific function of the design being tested. We are in the middle of a few new shifts which bring more standard DFT methodologies and practices into earlier steps in the design flow.

Biodata: Ron Press is the technical marketing director of the Tessent product family at Mentor Graphics Corp. As a 30-year veteran of the test and DFT industry, Ron has presented seminars on DFT and test throughout the world. He is a member of the International Test Conference (ITC) Steering Committee, and a Golden Core member of the IEEE Computer Society, and a Senior Member of IEEE. Ron has patents on reduced-pin-count testing, glitch-free clock switching, and on 3D DFT. Ron started his work in the test industry at Raytheon Company working on test and consulting throughout the company on test and built-in test. He co-developed the Testability Design Rating System (TDRS) for the US Air Force and received the Raytheon inventor's award for a system built-in test analysis system. Ron led the development of a state-of-the-art RF/digital tester at Harris RF when he joined them in 1995. He joined the Mentor DFT organization in 1997.

Keynote #4

Srinivas Chinamilli

Co-Founder & President, Tessolve

Title: Indian Semiconductor Test Industry: Evolution, Challenges and Opportunities

Abstract: - How we got here: from initial days of Texas Instruments, to all the top 10 semiconductor semiconductor companies having design centers in India. - How "Make in India" , "Digital India" and Global Semiconductor Manufacturing supply chain and Engineering is shaping the Semiconductor Industry today. - What opportunities the new technologies like IoT, smart communities and smart factories and connected world, AI machine learning, Autonomous cars, 5G related technologies bring to the Semiconductor Design and Test Industry for India.

Biodata: Srinivas has more than 25 years of experience in semiconductor Test and Product engineering. He has held management and technical positions at Cirrus Logic and was the Director of Worldwide Test engineering at Centillium Communications prior to joining Tessolve. He has extensive experience in the area of Mixed Signal and System on Chip test development, high volume production test and offshore test subcontractor management. He has received his B.E. (Electrical and Electronics) from Birla Institute of Technology and M.S. in Electrical engineering from the University of Southern California.

Keynote #5

Mahesh Kumashikar

Principal Engineer , Intel

Title: Design optimizations and challenges of computing systems

Abstract: The interconnected world and cloud computing demands insatiable performance from the warehouse scale computing infrastructure. Modern datacenters are composed of racks and racks of microprocessor units interconnected with massive data storage subsystems on a hyper fast network. These facilities demand huge power delivery and cooling requirements driving up the total cost of ownership. With datacenter operating costs dominated by energy, a  highly agile system design supporting both highest performance for peak demand and best-in-class performance/Watt overall is essential. Over the past decade, higher performance at silicon level have come from sophisticated processors becoming adaptive, self-optimizing units that squeeze ever-more performance at a given power budget. Silicon optimization, reliability, configurability, and management are therefore essential to increase performance to meet the computing demands. All these pose huge design challenges and opportunities in methodologies, configuration knobs, HVM & test domain to eke out last ounce of power-performance for datacenter.

Biodata: Mahesh Kumashikar is a technologist and principal engineer with Scalable CPU Development Group in Bangalore. He is currently working on defining next generation server products and most recently worked as technical lead on design of Broadwell-DE and Broadwell-SP server products. Before joining Intel India, Mahesh has worked in the US at Compaq’s Alpha processor design, Intel’s Itanium processor design, then SiCortex, a HPC startup, on low power MIPS server SoC, and AMD with 20+ years of industry experience. Mahesh received a M.S.E.E. from the University of Michigan in VLSI and a M.S. from Oregon Graduate Institute in Neural networks & DSP.

Keynote #6

Manabu Kimura

President, Cloud Testing Service, Advantest Group

Title: New concept of Semiconductor Testing, Challenge to IoT Era.

Abstract:Speaker will provide the basic views of semiconductor technology from a ATE supplier, and introduce the new concept of testing which connect semiconductor supply chains and life cycle through the cloud and big data.

Biodata:Manabu Kimura is the president of Cloud Testing Service, Inc. Japan, and Division Manager of CTS Business Unit of Advantest. He is leading new business model and evolutional products and systems for measurement and testing in electronics and semiconductor industry by utilizing recent ICT (Information and Communication Technology) and its infrastructure. Manabu has more than 20 year experiences in the semiconductor testing industry. Before he started CTS he was responsible for the global marketing of Memory ATE (Automatic Testing Equipment) in Japan HQ after led product engineering and marketing in North America decade of 2000s. Manabu holds a Master of Applied Physics from the University of Tsukuba.

ITC (INDIA)

Contact Details

Organizing Committee,  ITC-India 2017

Bangalore, Karnataka

India

Email: [email protected]