Accepted Submissions

Regular Paper -

#
Title
Decision
62
Addressing High Speed Memory Interface Test Quality Gaps in Shared Bus Architecture
ACCEPT
53
Parallel Field Test Architecture for Boot-ROMs in Safety-Critical SoCs
ACCEPT
49
Targeting Zero DPPM through Adoption of Advanced Fault Models and Unique Silicon Fall-out Analysis
ACCEPT
3
Accelerating GLS Simulation closure in DFT with Emulator Hardware
ACCEPT
35
A Novel Method to measure PLL Bandwidth in a 5G RF transceiver
ACCEPT
52
An Efficient Test Architecture for Concurrent Over Voltage Stress Testing (OVST) of Logic and Memory
ACCEPT
60
A Fast Robust Operation Mode invariant Frame-work for IR drop Prediction
ACCEPT
28
Method and Apparatus for Bug Free Rapid Silicon Bringup
ACCEPT
36
Comprehensive In-field Memory Self-Test and ECC Self Checker –Minimal Hardware Solution for FuSa
ACCEPT
47
16x Multisite, High Current and High Power density Test Solution for Power Protection Device
ACCEPT
15
Side-channel Analysis for Hardware Trojan Detection using Machine Learning
ACCEPT
32
Core Test Language based High Quality Memory Testing and Repair Methodology
ACCEPT
64
An Improved Test Pattern Reordering Framework Targeting Test Power Reduction
ACCEPT
65
Runtime Test Solution for Adaptive Power Optimization of Edge AI devices
ACCEPT

Academic And Research Track -​

a. Paper Presentation

#
Title
Decision
55
Top-Down analysis based performance failure bucketing for Pre-Silicon simulation
ACCEPT
68
Adapting AI into Low Power Testing
ACCEPT

b. Posters

#
Title
Decision
26
New Diagnostic March based Algorithmic Approach to Identify Stuck-At and Transition Faults
ACCEPT
11
Design of Low Power Bit Swapping BIST for IC Self Testing
ACCEPT

Test Reality Check -

a. User Experiences

#
Title
Decision
61
In Silicon Soft Error Injection DFT Technique for RAM REPAIR validation
ACCEPT
66
ScanDump made Easy! – An IJTAG based approach
ACCEPT

b. Data Blitz

#
Title
Decision
31
Yield Improvement techniques in Slow-Slow Devices during High Volume Manufacturing
ACCEPT
54
Innovative ways to address FPGA prototyping challenges of DFT IP
ACCEPT

c. Posters

#
Title
Decision
18
DFT STRATEGY FOR SAFETY DEVICES WITH AGING DETECTION REQUIREMENTS
ACCEPT
23
Effective defect screening techniques: The outright need of high-quality test
ACCEPT
25
Novel Approach for DFT Test time Reduction
ACCEPT
27
Left Shift & Correct by Construction DFT-RTL Design
ACCEPT
34
Design of low switching pattern generator for BIST architecture.
ACCEPT
39
High throughput Multiple Device Diagnostics for Hierarchical Test Designs
ACCEPT
44
Memory interface faults and the PPM requirements – The indecisive ram-sequential test
ACCEPT
50
Spyglass Netlist level Check – Methodology on Low Power Mixed Signal Design
ACCEPT
57
A Survey of Embedded Memory Testing
ACCEPT
59
A Novel Approach to minimize Coverage Drop between Pre-PnR to Post-PnR Netlist in SoC VLSI Design
ACCEPT
63
Automating silicon ATE bringup
ACCEPT
21
Configurable Scan Wrapper Architecture
ACCEPT