Sunday, July 22, 2018
8:30am-9:30am Registrations
Track 1 Track 2 Track 3
9:30 am - 11:00 am
(15 mins. Break)
11:15 am - 12:45 pm
T1: Machine Learning in Test
Yu Huang, Gaurav Veda; Mentor Graphics
T2: Automotive Reliability & Test Strategies
Zorian (Synopsys), Mariani (Intel);
T3: Test Access Mechanism (TAM) for Advanced SoCs
Punit kishore (Qualcomm), Jais Abraham (Qualcomm), Shamitha Rao (Mentor), Srijesh Parambath (Mentor)
12:45pm-1:45pm Lunch Break
1:45 pm - 3:15 pm
(15 mins. Break)
3:30 pm - 5:00 pm
T4: Are System Level Tests Unavoidable for High End Processors?
Dr. Adit D. Singh, Auburn University
T5: Recent Trends in Modelling and simulation of Defects in Analog Circuits and their Applications
Vijay Kumar Sankaran (Cadence), Lakshmanan Balasubramanian (Texas Instruments), Nadeem Tehsildar (Texas Instruments)
T6: Logic Encryption: A Design-for-Security Trust Methodology for Digital Integrated Circuits
Prof. Santanu Chattopadhyay, Rajit Karmakar; IIT-Kharagpur


Monday, July 23, 2018
8:00am-9:30am Registrations
9:30am-10:00am Inauguration/Welcome
10:00am-10:30am Keynote 1
10:30am-11:00am Keynote 2
11:00am-11:15am Tea/Coffee Break
11:15am-12:45pm Session 1 - Memory Test & Repair Session 2 - Debug & Diagnosis
12:45pm-1:45pm Lunch Break
1:45pm-3:15pm Demos Exhibits / Booth
3:15pm-3:30pm Tea/Coffee Break
3:30pm-5:00pm Session 4 - Automotive Test Session 4 - Mixed Signal & Analog Test
5:30pm-6:30pm Panel Discussion
6:30pm-9:30pm Dinner with Cultural Evening
Tuesday, July 24, 2018
8:30am-9:30am Registrations
9:30am-9:45am Welcome / Day 1 Summary
9:45am-10:20am Keynote 3
10:20am-10:55am Keynote 4
10:55am-11:15am Tea/Coffee Break
11:15am-12:45pm Session 5 - DFT Architecture Session 6 - Test Challenges
12:45pm-1:45pm Lunch Break
1:45pm-3:15pm Session 7 - Test Potpourri Session 8 - Standards
3:15pm-3:30pm Tea/Coffee Break Exhibits / Booth
3:30pm-5:00pm Demos
5:00pm-5:30pm Awards Function / Closing Ceremony

Paper Session

July 23 - Monday 11:15am-12:45pm
Session1: Memory Test & Repair
1-1. Improved RAM Sequential Tests for SoCs with Complex Memory Architectures
Wilson Pradeep and Prakash Narayanan
1-2. Automated Identification of Embedded Physical Memories using Shared Test Bus Access in IP Cores
Puneet Arora, Norman Card, Steven Gregor, Navneet Kaushik and Prashant Kulkarni.
July 23 - Monday 11:15am-12:45pm
Session2: Debug & Diagnosis
2-1. High Accuracy, Robust Multiple Defect Diagnosis Scheme
Bharath Nandakumar, Anil Malik, Sameer Chillarige, Anshul Kumar, Joe Swenton and Atul Chhabra.
2-2. Improving Diagnosis Resolution and Performance at High Compression Ratios
Sameer Chillarige, Atul Chhabra, Anil Malik, Bharath Nandakumar, Joe Swenton and Krishna Chakravadhanula.
2-3. TBD (Invited)
July 23 - Monday 3:30pm-5:00pm
Session3: Automotive Test
3-1. Enhancing Automotive Self-Test with Embedded Distributed Programming
Carl Wisnesky II and Patrick Gallagher.
3-2. Breaking Test Coverage and Test Cost Barrier for Safety Critical Automotive Designs Targeting Zero DPPM
Wilson Pradeep, Aravinda Acharya and Nikita Naresh.
3-3. DFT strategy in automotive devices with low cost testing requirements
V Srinivasan, Sabyasachi Das, Manish Sharma and Tripti Gupta.
July 23 - Monday 3:30pm-5:00pm
Session4: Mixed Signal & Analog Test
4-1. Modeling and Simulation of Defects in Analog Circuits: Fault Modeling, Simulation and Coverage Calculation
Vijay Kumar, Lakshmanan Balasubramanian, Victor Zhuk and Nadeem Husain Tehsildar.
4-2. RF Senstivity test(7.5GHz) in non RF configuration using on board components
Sivapavan Anala, Purnachandra N, Jagadish Chandrasekaran and Srinivasan Chandrasekaran.
4-3. Challenges in analog loopback testing for RF transceivers
Nagarajan Viswanathan, Vidhya Lakshmi M, Nithin Gopinath, Shuhood Mohamed and Subbarao Nalluri.
July 24 - Tuesday 11:15am-12:45 pm
Session5: DFT Architecture
5-1. Testability of High-speed On-Chip Interconnect on ATE
Vishwajit Reddy, Amanulla Khan, Pradeep Bhat, Vinod Pagalone, Punj Pokharel and Suhas Satheesh.
5-2. A Novel Test Wrapper Architecture Design for Scan as well as Functional Test
Khushboo Agarwal and Ahmet Tokuz.
5-3. IP Design for Test Considerations for an Automotive End Application
Teresa McLaurin and Ke Peng.
July 24 - Tuesday 11:15am-12:45 pm
Session6: Test Challenges
6-1. HBM operation and testing challenges
Narayanaswamy Muniyappa, Arun Kumar Chockalingam and Neelakandan Eswaran.
6-2. Test and Characterization of High Speed I/Os
Harsh Baghel, Vinod Kolluru and Krishna Rajan.
6-3. Test of Low Cost Microcontrollers: Challenges and Solutions (Invited)
Texas Instruments
July 24 - Tuesday 1:45pm-3:15pm
Session7: Test Potpourri
7-1. Post Fabrication Fix for RF DIB Design Problems
Jagadish Chandrasekaran, Kandhan Rajakumar, Srinivasan Chandrasekaran and Gowrishankar Ilankumaran.
7-2. Hardware Trojan Prevention and Detection Used in Integrated Circuits
Jayanthi Daniel and Joshi Hrushikesh.
7-3. Power Efficient Circuit implementation for High Speed Digital Design
Renuka Nagapurkar.
July 24 - Tuesday 1:45pm-3:15pm
Session8: Standards
8-1. Practical aspects of a IEEE 1687 (Invited)
Cadence Design Systems, GlobalFoundries
8-2. ISO 26262 (Invited)
Mentor Graphics