Tutorial Schedule

­ Day 1: Sunday, July 9, 2017

 

TRACK-1

TRACK-2

TRACK-3

9:30am - 11:00 am
(15 mins. break)
11:15am - 12:45pm

T1 : Testing, Tuning and Built-In Self-Adaptation Techniques for Mixed-Signal/RF Circuits and Systems

Professor Abhijit Chatterjee, Georgia Institute of Technology

T2: Adaptive Test Methods Targeting "Zero Defect" IC Quality and Reliability Dr. Adit D. Singh, Auburn University

T3: DFT for Low Power Designs: Challenges and Solutions Qualcomm & Mentor Graphics

12:45pm - 1:45pm

Lunch Break

1:45 pm - 3:15 pm
(15 mins. break)
3:30am - 5:00pm

T4: Test and Productization of IoT TESSOLVE Semiconductor Pvt Ltd

T5: Practical aspects of a physically-aware volume diagnosis methodology Cadence Design Systems

T6: Challenges in Testability for Security: A State-of-the-Art Perspective Debdeep Mukhopadhyay, IIT Kharagpur

 

RF/ANALOG TESTING FOCUS

Zero Defect & Diagnosis

Security & Low power

combination of Acadamia & Industry

combination of Acadamia & Industry

combination of Acadamia & Industry

 

Technical Program Schedule

Day 2: Monday, July 10, 2017

7:30am-9:00am

Registrations

9:00am-9:30am

Inauguration/Welcome

9:30am-10:15am

Keynote 1: Mobile Evolution - Challenges for Test, Srini Maddali, Vice-President (Technology), Qualcomm

10:15am-11:00am

Keynote 2: Next Generation CMOS Image Sensor (CIS) : Test and Reliability challenges for new emerging applications, Gianluca Colli, Vice President & GM, Consumer Solutions Division – Image Sensor Group, ON Semiconductor

11:00am-11:25am

Tea/Coffee Break

11:25am-12:10pm

Keynote 3: Why You Want Test to Become an Afterthought, Again, Ron Press, Technical Marketing Director – Silicon Test Solutions group, Mentor Graphics

12:10pm-12:45pm

Invited Talk: Exposing Some Myths about Fault Coverage, Peter Maxwell, ON Semiconductor

12:45pm-1:45pm

Lunch Break

1:45pm-3:15pm

Session 1: Processor & Memory Test

Session 2: Test Challenges

 

Exhibits / Booth

 

3:15pm-3:30pm

Tea/Coffee Break

3:30pm-5:00pm

Session 3: IoT

Session 4: Testability & ATPG

5:30pm-6:30pm

Panel Discussion

7.00pm onwards

Networking Dinner (Open for all participants)

 

Day 3: Tuesday, July 11, 2017

8:30am-9:30am

Registrations

9:30am-10:15am

Keynote 4: Indian Semiconductor Test Industry: Evolution, Challenges and Opportunities, Srinivas Chinamilli, Co-Founder & President, TESSOLVE SEMICONDUCTOR PVT LTD

10:15am-11:00am

Keynote 5: Design optimizations and challenges of computing systems , Mahesh Kumashikar, Principal Engineer , Intel

11:00am-11:25am

Tea/Coffee Break

11:25am-12:10pm

Keynote 6: New concept of Semiconductor Testing, Challenge to IoT Era., Kimura Manabu, President, Cloud Testing Service, Advantest Group

12:10pm-12:45pm

Invited Talk: The True Cost of Test , Rubin Parekhji, Texas Instruments

12:45pm-1:45pm

Lunch Break

1:45pm-3:15pm

Poster Session

Exhibits / Booth

3:15pm-3:30pm

Tea/Coffee Break

3:30pm-5:00pm

Session 5: Mixed Signal & IJTAG Test

Session 6: Reliability

5:00pm-5:30pm

Awards Function / Closing Ceremony

 

 

 

Session Details

July 10 - Monday 1:45-3:15 pm

Session 1: Processor & Memory Test

Session Chair: Vikram Kuralla

1-1 The DFT Challenges and Solutions for the ARM® MaliTM-Mimir GPU

Teresa Mclaurin and Prashant Kulkarni

1-2 High Performance CPU Design and associated HVM/Test Challenges (Invited Talk)

Shridhar Bhendi, Intel

1-3 Effective Memory Repair Solution in Power -Domain Based Designs

Jay Shah and Bharat Londhe


July 10 - Monday 1:45-3:15 pm

Session 2: Test Challenges

Session Chair: Nagesh Tamarapalli

2-1 Functional Safety (Invited Talk)

Prashanth/Ashish, Texas Instruments

2-2 Holistic approach to DFT: Component to System (Invited Talk)

Sivakumar, Keysight

2-3 DFT design challenges for next generation 7nm FinFET applications (Invited Talk)

Jeanne Trinko Mechler, GLOBALFOUNDARIES


July 10 - Monday 3:30-5:00 pm

Session 3: IoT

Session Chair: Pramod Notiyath

3-1 IoT-Creating a Cost Effective High MultiSite RF Solution (Invited Talk)

Sujanandan Tuttipattu, Advantest

3-2 Evolutionary Value Added, Accelerate New Product Time-to-Market (Invited Talk)

Koh Chai Leong Daniel, Advantest

3-3 Post Silicon Validation of Power Management Modules for Low Power, Battery Operated Wireless Devices for IoT: A Comprehensive Approach

Prathap Ghorpade, Murugesh Subramaniam, Harish Ramesh, Manoja Vinnakota, Asaf Even-Chen and Asaf Carmeli


July 10 - Monday 3:30-5:00 pm

Session 4: Testability & ATPG

Session Chair: Hasanuzzaman Sheikh

4-1 X Elimination to Improve the Quality of Scan Compression

Mahmut Yilmaz, Animesh Khare, Rahul Garg, Mayank Parasrampuria, Nitin Yogi, Jaison Kurien, Rahul P R, Shantanu Sarangi and Krishna Rajan

4-2 Observation-Point identification based on Signal Selection Methods for Improving Diagnostic Resolution

Subhadip Kundu, Kanad Basu and Rohit Kapur

4-3 Robust and Efficient Cell Aware Test Model Generation Methodology

Animesh Khare, Jaison Kurien, Farideh Golshan, Jon Colburn, Deepak K G, Rejeesh Vijayan, Rahul P R, Francisco Da Silva and Krishna Rajan


July 11 - Tuesday 3:30-5:00 pm

Session 5: Mixed Signal & IJTAG Test

Session Chair: Pramod Notiyath

5-1 DFT for measuring and trimming Frequency response of IF receiver

Pradeep Nair, Aniket Datta, Rajendrakumar Joish and Arun Mohan

5-2 IJTAG based BIST for Video DAC testing

Kamlesh Pandey

5-3 Improved Automation in Parallel Tests for Embedded IPs using Broadcast Test Generation with IEEE 1687

Rajesh Khurana, Krishna Chakravadhanula, Dhruv Dua, Divyank Mittal and Balveer Singh Koranga


July 11 - Tuesday 3:3-5:00 pm

Session 6: Reliability

Session Chair: Krishna Chakravadhanula

6-1 Reliability concerns of Integrated Chips due to Electromigration (Invited Talk)

Govind Saraswat, Oracle

6-2 Cognitive Approach to Support Dynamic Ageing Compensation

Souhir Mhira, Vincent Huard, Alain Bravaix, Ahmed Benhassain, Florian Cacho, Sylvie Naudet, Abhishek Jain and Chittoor Parthasarathy

6-3 An overview of Design and Reliability of Gallium Nitrite HEMT Power Devices (Invited Talk)

Mayank Shrivastava, IISc


 


Invited Talks


 

Exposing Some Myths about Fault Coverage

Peter Maxwell, ON Semiconductor

Abstract: This talk addresses some commonly held misconceptions about fault coverage. It is demonstrated that, when taking into account transistor level gate implementations, a simple fault coverage value does not necessarily correlate to the goodness or badness of a test. Many different combinations with the same fault coverage can have very different effectiveness in detecting gate defects. It is also shown that depending on modelling, there can be a wide range in the number of test patterns required to achieve a given coverage. Finally, weighted versus unweighted coverages are examined, highlighting the need to weight faults with their probability of occurrence.

Biodata: Peter Maxwell works for ON Semiconductor, where he is responsible for test and DFT for CMOS image sensors. He received the B.Sc. and M.Sc. degrees in Physics from the University of Auckland, New Zealand, and the Ph.D. degree in EECS from the Australian National University. His interests include test methodologies, design for testability, and their application for yield improvement, diagnosis, quality and test time reduction. He spent many years co-ordinating test experiments and was one of the first to widely publish industrial data on test effectiveness. He is a Fellow of the IEEE.


Reliability concerns of Integrated Chips due to Electromigration

Govind Saraswat, Oracle

Abstract: Reliability is an important aspect of a successful microelectronics chip. A chip can have fastest and largest number of cores but it wouldn’t be of much use if it fails after an hour of operation. Chip reliability can be broadly classified into two types: manufacturing defects and wear-out issues. Some of the wear-out failure mechanisms that exist are time-dependent dielectric breakdown, hot carrier injection, negative bias temperature instability and electromigration (EM). EM is a physical phenomenon, where mass transport of metal atoms occurs as a result of momentum transfer due to random bombardment of the conducting electrons. This talk highlights the theory behind current methods which are used for performing EM verification for VLSI interconnects. It also covers a recently reported method which provides an accurate metric for EM reliability for the entire design thus it is not affected by the inherent pessimism existing in the state-of-art methods used by the industry. In this method, failure rates are computed for each wire interconnects and accumulated in the design. This talk will delve into the relationship between the current density in a wire; relevant physical parameters and the failure rate of the metal interconnect, finally culminating in EM reliability equation.

Biodata: He received his Bachelors in Electrical Engineering from IIT Delhi, India in 2007 and PhD in Electrical Engineering from University of Minnesota, USA in 2014. He has been working with the hardware division of Oracle since then. His research interest includes reliability of microprocessors, statistical and stochastic modeling, signal processing, and filtering.


An overview of Design and Reliability of Gallium Nitrite HEMT Power Devices

Mayank Srivastava, IISc, Bangalore

Abstract: Gallium Nitride Based Power electronic devices are projected to cross $1B mark by 2022 and $5B mark by 2025 with a market dominance in medium voltage segment. However, the question is would GaN enjoy a similar development roadmap that Si power devices have enjoyed and can it leverage learning/know-how developed from Si power device technology. If not, what is required to be addressed at this stage of technology development? This talk is divided into three parts. In the first part, I will give a brief review of techno-commercial aspects of GaN HEMT technology and design aspects of the same. The second part will focus on comprehensive TCAD methodology and TCAD based design approach for GaN HEMT technology, in a tone similar to what Si has enjoyed in the past. In the last part, I will stress on how critical reliability-aware design is for GaN HEMT technology while highlighting some new learnings we have acquired both regarding long term reliability of commercial GaN devices, as well as SOA like short time device reliability of in-house developed GaN devices.

 

Biodata: Prof. Mayank Shrivastava received his Ph.D. degree from Indian Institute of Technology Bombay. He has over 70 international publications and 35 patents. Prof. Shrivastava’s current research deals with experimentation, design, and modeling of beyond CMOS devices using Graphene and TMDCs, wide bandgap material based power semiconductor devices and ESD reliability in advanced and beyond CMOS nodes. He had held positions in Infineon Technologies, Munich, Germany; Infineon Technologies, East Fishkill, NY, USA; IBM Microelectronics, Burlington, VT, USA; Intel Mobile Communications, Hopewell Junction, NY, USA; and Intel Corp., Mobile and Communications Group, Munich, Germany between 2010 and 2013. He joined Indian Institute of Science Bangalore as a faculty member in September 2013. He is among the first recipient of Indian section of American TR35 award (2010). He is also the first Indian to receive IEEE EDS Early Career Award (2015). In addition to this he is an IEEE Senior Member and has received several other awards and honors including few best research paper awards; excellence in research award for his Ph.D. thesis in 2010 and industrial impact award from IIT Bombay in 2008. More details related to his group or work can be found at http://mayank.dese.iisc.ac.in/

 


Holistic approach to DFT: Component to System

Sivakumar Vijayakumar, Keysight Technologies

Abstract: As the complexities of the semiconductor chip and PCB design complexities are increases, testing of components to systems, the quintessential need for a quality manufacturing test is becoming a challenge. This makes it essential to have a good ‘Design for Test’ (DFT) from a component to a system to ensure a robust structural test all through. 1. What are the benefits of adding DFT elements? 2. What are the aspects to be considered for enhancing ‘DFT’? 3. What is the value across the Product Life Cycle - chip to the system? 4. How can the DFT be best leveraged across phases of Product Life Cycle? By answering the above questions, we will conclude on how a holistic approach to DFT can enhance testability and quality from chip to a system. .

Biodata: A Technical Marketing Engineer with Keysight Technologies, Sivakumar Vijayakumar’s area of focus is on Boundary Scan Based Board Testers. Sivakumar’s responsibilities include - investigating customer’s technology needs; defining and developing new test solutions/features; and ensuring customers adoption of new technology solutions. He is involved in training the field teams and works closely with the team to assist in pre-sales activities. He holds a Bachelor of Engineering in Electronics from Bangalore University. Prior to joining Keysight Technologies, Sivakumar has held various engineering positions with leading electronic service providers, original equipment manufacturers and semiconductor sectors for the past 16 years.


IoT-Creating a Cost Effective High MultiSite RF Solution

Sujanandan Tuttipattu, Advantest

Abstract: The Internet of Things is a system, where communication between each other occurs over the internet and can transfer and act on data, with minimal interaction. With the on-surge of Internet of Things (IoT) wave, huge arrays of low-cost RF devices need to be tested and brought to market in shortest time. At the same time, the pressure on reducing ASP and COT is always a key factor. To test these low-cost RF devices, there is a need to go for higher multi-site count, for example, 16 sites. To handle high multi-site test challenges, the ATE needs to have sufficient resources and an efficient way of utilizing them. This paper provides the solution on how to test a 16-site RF SOC device with special features.

Biodata: Sujanandan TR is working as a Staff Application engineer in Advantest, Singapore. He received his Bachelor Degree from Anna University, India and Master’s Degree from NUS, Singapore. He has been working in semicon industry for the past 20 years. He is the key person in bringing up Advantest’s state of art tester “WaveScale” system in to production. His experience includes, presales, production support, application development and debug on wide variety of digital, mixed signal and RF devices. In his free time, he spends time with family and reading books.


Evolutionary Value Added, Accelerate New Product Time-to-Market

Koh Chai Leong Daniel, Advantest

Abstract: Analog and mixed-signal ICs are critically important in enabling the increasing performance, higher accuracy and longer reliability of today's smart electronics. Our new monolithic test solution eliminates the high cost, complex set up and long lead times required when using several kinds of measurement instruments to test these devices. Designed for use in both engineering and volume-production environments, the EVA100 solution provides features for seamless & quick time-to-market for IoT devices while achieving highly precise measurements & improving testing efficiency.

Biodata: Daniel Koh is currently the Business Development manager in Advantest, Singapore, focusing on new products. He has been with Advantest since 1995, beginning as an application engineer, and has worked in other positions as Sales account manager & Application manager. His experience includes pre-sales, application & production support on Advantest platform, as well as customer account management. He graduated with a Bachelor Degree in Engineering from the Nanyang Technological University, Singapore.


High-Performance CPU Design and associated HVM/Test Challenges

Shridhar Bendi, Intel

Abstract: Speaker will provide basics around building high-performance CPU and will cover non-traditional challenges associated with Testing and Productizing SoCs. Unlike traditional ASICs, high-end chips have aggressive Power Management states (varying P-States, C-States). And this problem gets compounded further when with on-die Voltage Regulators. There would be mention about growing pains in building SoCs on evolving process node and associated design resilience to work around varying material type over time.

Biodata: Shridhar Bendi serves as DFx and Post-Si Debug Lead for Server SoCs designed out of Intel, Bangalore. His most recent contributions include productizing BDX-DE Micro Server and BDX-ML Mainline Servers built on Intel’s 14nm Process node. Prior to joining Intel India design center, he has worked in US with AMD, Texas Instruments, Cyrix and Intel with industry experience of 20+ years of experience. Currently he is Principal Engineer with SDG-India, Bangalore working on the next generation Servers.


DFT design challenges for next generation 7nm FinFET applications

Jeanne Trinko Mechler, GLOBALFOUNDRIES, Essex Junction, VT

Biodata: Jeanne Trinko Mechler, is a fellow in the GLOBALFOUNDRIES ASIC worldwide design organization. After 30 years of chip design experience working for the IBM Systems & Technology Group in Essex Junction, VT, she joined GLOBALFOUNDRIES in 2015. She holds patents and has published papers in the areas of design for test, reliability, failure analysis, and SOC design. She has completed more than 35 custom logic designs and is currently working on 7nm and 14nm FinFET chip design. She specializes in networking chips and is an author of the engineering textbook High-Speed SerDes Devices and Applications. She received the M.S. and B.S. in electrical engineering from the University of Vermont in 1989 and 1985 respectively, and the M.S. in engineering management from the National Technological University in 1992.


Functional Safety

Prasanth V and Ashish Vanjari, Texas Instruments

Abstract: Automotive sector is seeing fast paced growth, with ever increasing demand for Integrated Circuit (IC) to address challenges of safety, comfort, performance and automation. With increased penetration of ICs, the risk associated with its failures leading to accidents is elevated. ISO26262 functional safety standard provides guidance on containing these risks to an acceptable level. This talk gives an overview of various requirements as laid out by ISO26262. Since the standard focuses on vehicle level functions, interpreting of the same becomes challenging for an IC design engineer. This talk will attempt to bridge this gap by giving a brief overview of how system level functional safety requirements can be translated to IC design requirements. The talk also provides safety analysis techniques deployed during the design phase to ensure that the functional safety requirements are met.

Biodata: Prasanth V is a Functional Safety Architect at Texas Instruments. He is a TUV SUD certified Functional Safety Professional and is part of the United States Technical Advisory Group (USTAG) for ISO26262 which undertakes the development and revision of the automotive functional safety standard. He has worked as a DFT lead and now focuses on IP architecture and functional safety. His research interests include design of low cost reliable systems, design of on-line test techniques, etc. He has six patents (granted/filed) and twenty six publications covering IEEE conferences, vendor conferences and TI internal symposiums including one best paper award. He holds a Master’s degree from Indian Institute of Science, Bangalore.

Ashish Vanjari is a Functional Safety Technologist at Texas Instruments. He is a TUV SUD certified Functional Safety Professional and is part of the United States Technical Advisory Group (USTAG) for ISO26262. As part of standards committee member, he has contributed to the topic of fault injection in 2nd revision of ISO26262. In his over 16 years at TI, he has worked as a Design Verification Lead and now focuses on safety analysis and safety certification of SoC. He has given multiple talks internally and externally on functional safety and conducted trainings for professionals on topic of functional safety. He holds a Bachelor’s degree from Pune University.


The True Cost of Test

Rubin Parekhji, Texas Instruments

Abstract: Test (and DFT) mean different things to different people at different times. Depending upon the maturity of the design, and the DFT and test solution, it is either an overhead, or an enabler or a differentiator. In this talk, we will illustrate through a few examples how new test methods can significantly help in cost reduction. When leveraged suitably, the cost due to these methods is no longer just the overhead cost, but is now part of the overall cost incurred to bring product differentiation. “The True Cost of Test” is therefore likely to be much lower than what is normally projected.

Biodata: Rubin Parekhji has been with Texas Instruments, Bangalore, since 1996, where he has led and mentored DFT teams on various design and test technology projects across multiple product groups. More recently, he has been in Kilby Labs and Analog Engineering Operations, working on low cost test methods and test entitlement targets. He has published regularly at leading conferences, has mentored a large number of students, and has several issued patents. He has a Ph.D. from Indian Institute of Technology, Bombay, India.


 

 

ITC (INDIA)

Contact Details

Organizing Committee,  ITC-India 2017

Bangalore, Karnataka

India

Email: navin.bishnoi@globalfoundries.com